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ABSTRACT: A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: The availability of SOI from silicon foundries is making SOI a viable option for implantable electronics devices. The field has some specific needs that are different to many conventional electronics applications. Low power operation is essential but with intermittent high power requirements and the need for long term reliability. Conversely, circuit operating speed requirements are often extremely low; including monitoring at only a few KHz. Data storage (memory) requirements may also be relatively low. Furthermore, the operating temperature range of implanted devices is low compared to many non-implantable applications. These requirements together are assessed against the unique attributes of silicon on insulator (SOI) as a semiconductor material of choice for this environment, compared to that of conventional 'bulk' silicon.
Engineering in Medicine and Biology Workshop, 2007 IEEE Dallas; 12/2007
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ABSTRACT: This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.
SOI Conference, 2007 IEEE International; 11/2007
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G. Knoblinger,
M. Fulde,
D. Siprak,
U. Hodel,
K. Von Arnim, T. Schulz,
C. Pacha,
U. Baumann,
A. Marshall,
W. Xiong,
C.R. Cleavelin,
P. Patruno,
K. Schruefer
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ABSTRACT: In this paper we present for the first time essential building blocks for RF circuits in an advanced FinFET technology. Voltage controlled oscillators (VCOs) and a low noise amplifier (LNA) have been realized.
SOI Conference, 2007 IEEE International; 11/2007
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C. Pacha,
K. von Arnim,
F. Bauer, T. Schulz,
W. Xiong,
K.T. San,
A. Marshall,
T. Baumann,
C.R. Cleavelin,
K. Schruefer,
J. Berthold
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ABSTRACT: Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.
37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
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F. Bauer,
K. von Arnim,
C. Pacha, T. Schulz,
M. Fulde,
A. Nackaerts,
M. Jurczak,
W. Xiong,
K.T. San,
C.-R. Cleavelin,
K. Schrufer,
G. Georgakos,
D. Schmitt-Landsiedel
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ABSTRACT: We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European; 10/2007
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N. Collaert,
A. De Keersgieter,
A. Dixit,
I. Ferain,
L.-S. Lai,
D. Lenoble,
A. Mercha,
A. Nackaerts,
B.J. Pawlak,
R. Rooyackers, T. Schulz,
K.T. Sar,
N.J. Son,
M.J.H. van Dal,
P. Verheyen,
K. von Arnim,
L. Witters,
De Meyer,
S. Biesemans,
M. Jurczak
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ABSTRACT: Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V<sub>T</sub> statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.
37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
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K. von Arnim,
E. Augendre,
A.C. Pacha, T. Schulz,
K.T. San,
F. Bauer,
A. Nackaerts,
R. Rooyackers,
T. Vandeweyer,
B. Degroote,
N. Collaert,
A. Dixit,
R. Singanamalla,
W. Xiong,
A. Marshall,
C.R. Cleavelin,
K. Schrufer,
M. Jurczak
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ABSTRACT: This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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ABSTRACT: A multi-gate CMOS technology for low-power applications with highly competitive digital performance is presented. Ring oscillators with metal gates and undoped fins are measured with high yield demonstrating the capability of large scale integration. An inverter delay of 15 ps and 0.5 nA/stage off-current at V<sub>dd</sub>=1.2 V shows an improved leakage-performance trade-off compared to 65 nm low-standby power CMOS technologies. Scalability to 32 nm and beyond is shown.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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ABSTRACT: Electrostatic discharge (ESD) characteristics of fully depleted FinFET devices are presented and compared to planar structures manufactured in the same multiple-gate FET Technology. FinFET-type MOS devices in breakdown mode are found to show an unprecedented sensitivity to ESD stress, while planar devices and FinFET gated diodes perform reasonably and with - characteristics beneficial for ESD protection.
IEEE Transactions on Device and Materials Reliability 04/2007; · 1.54 Impact Factor
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ABSTRACT: N-channel trigate SOI MOSFETs have been irradiated with <sup>60 </sup>Co gamma rays at doses up to 6 Mrad(SiO<sub>2</sub>). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO<sub>2</sub>), the current drive reduction in the same devices is 10% if V<sub>G</sub>=0 V during irradiation and 20% if V<sub>G</sub>=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO<sub>2</sub>)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed
IEEE Transactions on Nuclear Science 01/2007; · 1.45 Impact Factor
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ABSTRACT: An increase in threshold voltage is observed in ultra-thin body MuGFET (multi-gate FET) devices. The threshold increase is
due to of lack of carriers at the classical threshold definition. A sufficient amount of carrier build-up requires additional
gate voltage (0.12V in our experiment).
12/2006: pages 159-164;
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ABSTRACT: Evidence of a one-dimensional subband formation is found in Pi-gate SOI MOSFETs at room temperature as oscillations are found in the I<sub>D</sub>(V<sub>G</sub>) characteristics. These oscillations correspond to an intersubband scattering. Even though the height-to-width ratio of the silicon fins is equal to five, the device behavior is better described by a one-dimensional semiconductor theory than by a two-dimensional gas model
IEEE Electron Device Letters 10/2006; · 2.85 Impact Factor
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ABSTRACT: The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performance is studied. For relatively low levels of bending-induced surface strain (~ 0.1%), significant enhancements in the driving current can be achieved and maintained with gate-length scaling. This makes package strain a potentially attractive approach to enhancing MuGFET-based CMOS performance at low cost. For bending-induced strain, the enhancements in electron mobility and (110) hole mobility are well predicted by the piezoresistance model using the coefficients for bulk-Si, but the impact of stress on (100) hole mobility is more complex
IEEE Electron Device Letters 09/2006; · 2.85 Impact Factor
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W. Xiong,
C.R. Cleavelin,
P. Kohli,
C. Huffman, T. Schulz,
K. Schruefer,
G. Gebara,
K. Mathews,
P. Patruno,
Y.-M. Le Vaillant,
I. Cayrefourcq,
M. Kennard,
C. Mazure,
K. Shin,
T.-J.K. Liu
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ABSTRACT: In this letter, it is shown that for fin widths down to < 20 nm, strain can be retained in patterned strained-silicon-on-insulator (sSOI) films and is correlated to mobility enhancements observed in FinFET devices. NMOS FinFET mobility is improved by 60% and 30% for [110]/<110> and (100)/<100> fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for [110]/<110> fins, it is enhanced by up to 30% for (100)/<100> fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients.
IEEE Electron Device Letters 08/2006; · 2.85 Impact Factor
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J.-P. Colinge,
L. Floyd,
A.J. Quinn,
G. Redmond,
J.C. Alderman,
W. Xiong,
C.R. Cleavelin, T. Schulz,
K. Schruefer,
G. Knoblinger,
P. Patruno
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ABSTRACT: Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6×10<sup>17</sup> cm<sup>-3</sup>. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO<sub>2</sub> interfaces, shows up at temperatures lower than 150 K.
IEEE Electron Device Letters 04/2006; · 2.85 Impact Factor
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C. Pacha,
K. von Arnim, T. Schulz,
Weize Xiong,
M. Gostkowski,
G. Knoblinger,
A. Marshall,
T. Nirschl,
J. Berthold,
C. Russ,
H. Gossner,
C. Duvvury,
P. Patruno,
R. Cleavelin,
K. Schruefer
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ABSTRACT: Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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J.-P. Colinge,
A.J. Quinn,
L. Floyd,
G. Redmond,
J.C. Alderman,
Weize Xiong,
C.R. Cleavelin, T. Schulz,
K. Schruefer,
G. Knoblinger,
P. Patruno
[show abstract]
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ABSTRACT: Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I<sub>D</sub>(V<sub>G</sub>) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm<sup>2</sup>/Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.
IEEE Electron Device Letters 03/2006; · 2.85 Impact Factor
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A. Marshall,
M. Kulkarni,
M. Campise,
R. Cleavelin,
C. Duvvury,
H. Gossner,
M. Gostkowski,
G. Knoblinger,
C. Pacha,
C. Russ,
K. Schruefer, T. Schulz,
K. VonArnim,
B. Wilks,
W. Xiong
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ABSTRACT: With trends toward smaller geometries and improved circuit performance continuing, an option being investigated is multigate FETs on SOI substrates. SOI lends itself to SOC systems due to its inherently lower noise and ease of integration of analog, digital, RF and power circuits. A critical analog circuit requirement is accurate current mirroring. Here characteristics of fully depleted FinFET current mirrors are presented. Silicon FinFET current mirrors and their bulk planar counterparts have similar performance and matching: a vital requirement for analog circuitry on this type of material.
Architecture, Circuits and Implementtation of SOCs, 2005. DCAS '05. Proceedings of the 2005 IEEE Dallas/CAS Workshop:; 11/2005
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T. Schulz,
W. Xiong,
C.R. Cleavelin,
K. Schruefer,
M. Gostkowski,
K. Matthews,
G. Gebara,
R.J. Zaman,
P. Patruno,
A. Chaudhry,
A. Woo,
J.P. Colinge
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ABSTRACT: Fin thickness non-uniformity is a potential shortcoming of vertical multiple-gate devices such as FinFETs and tri-gate FETs. In this paper a test structure with intentionally misaligned gates is used to investigate the sensitivity of electrical characteristics on fin thickness variations.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
