ABSTRACT: We have developed highly reliable low resistance copper contact technology for CMOS device beyond 32nm node. Cu contact is expected to reduce contact resistance but degradation of device performance caused by Cu diffusion into Si and filling failure of high aspect ratio contact hole using current BEOL Cu process are concerned. The excellent Cu diffusion barrier endurance of CVD TiN/PECVD Ti stacked barrier metal is confirmed by backside SIMS, and it is considered that micro grain TiN layer formed by NH3 plasma treatment after Ti CVD step would act as Cu barrier. As a result, junction leak caused by Cu diffusion is effectively suppressed. Furthermore, additional CVD Ru on the barrier metal improves Cu filling capability drastically. Cu contact integrated with CVD Ru and CVD TiN/PECVD Ti achieves contact resistance reduction of about 50% compared with current W contact with MOCVD TiN/PVD Ti.
Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008