ABSTRACT: In recent years, advances in information technology are taking place with tremendous speed. Especially in electronic devices, pursuit of reduction in size and weight, sophistication, and increase in speed never seem to stop. Since the first computer chip was invented in the 1970¡¯s, it only took less than 30 years for the spread of computers to regular households. In order to support such rapid growth, electronic device technology has been put under great pressure, and numerous problems have been raised one after another. Uses not only in computers but also in cellular phones, portable music players, and recently in car technologies, electronic devices are in need to be produced in diversity in terms of forms, composing materials, and environment in which they are used. Also in order to improve in function, device structures are increasing in complexity. Along these stated above, there is absolute need to consider about environmental issues, such as reducing use of load, recycling, and long duration life designing. Other than gaining speed in advancing technology, reliance designing is an important issue as well. Recently, problems in mounting reliability include delamination and fatigue in adhesive jointing structures. One of the most significant technologies in terms of reliance improvement in mounting structures is the use of underfill materials between the chips and the substrate that lies underneath. First, using underfill reduces the impact caused by mismatches in the coefficient of thermal expansion (CTE) between the silicon chip and the attaching substrate when there are changes in the temperature of the environment, such as heating up of the circuit. Second, underfill reduces the impact of physical shocks and bending. In surface mounting structures where the chip is attached directly to the substrate with solder joints, the solder joints themselves represent the weakest points in the structure and therefore are most susceptible to stress failure¡ªobviously the most critical problems for a failure at any interconnect point leads to failure of the functionality of the whole circuit. By tightly adhering the chip, solder balls and substrate using underfill, stresses and strains are redistributed, and problems at weak points can be greatly reduced. Other than the advantages stated above, underfill materials can be used to protect structures from moisture and contamination. For these reasons, the use of underfill materials is a technology necessary in electronic device production. However, on the other hand, there are problems caused from using underfill. By underfilling the structure, in addition to the conventional problems such as the weakness of solder joints at both the chip side and the substrate side, stress is generated at the chips-underfilll interface and the undefill-substrate interface as well. This leads to concerns about interfacial delamination and is a critical issue in terms of reliability. Including the complex structure around interfaces expected to cause delamination, different destruction modes such as chips cracking and solder cracking effect each other and eventually result in the destruction of the whole structure. And this leaves necessity for unified assessment of the destruction modes, and for predicting the reliability of the structure. Structural materials are often assumed to be bond to each other perfectly. However, as shown in the bottom figures, bonded interfaces are constructed partly, and localized nonlinear deformations are often appears. To evaluate the interfacial strength, microstructure of interfaces should be comprehended. In this study, the strength evaluation technique on the resin field side is examined. In particular, microstructure of interface is¡¡the main factor. Then, observation of interfacial structure by using SEM during low cycle mechanical fatigue clarifies the microstructure and the interfacial model with complex structure is constructed. In addition, destruction behavior in micro interfacial area is clarified by doing the analysis that considers the destruction process.
Proceedings of 12th International Workshop on Thermal investigations of ICs, THERMINIC 2006, p. 107-111.