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ABSTRACT: In the past, we have made use of infrared CCD camera to take pictures of vein for vein authentication. However, mounting infrared CCD camera for electrical device is dangerous due to the problem of privacy invasions. In addition, there have been registration problem which lower the correlation. Then, we propose a method that visualizes vein using color information subpixel level image registration technique. These methods do not require infrared CCD camera, and furthermore. Consequently, we create a high-accuracy authentication system without the use of infrared CCD camera.
ICCAS-SICE, 2009; 09/2009
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T. Yaegashi,
T. Okamura,
W. Sakamoto,
Y. Matsunaga,
T. Toba,
K. Sakuma,
K. Gomikawa,
K. Komiya,
H. Nagashima,
H. Akahori, [......],
H. Kutsukake,
M. Sakuma,
H. Maekawa,
Y. Ishibashi,
K. Sugimae,
H. Koyama,
T. Izumida,
M. Kondo,
N. Aoki, T. Watanabe
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ABSTRACT: 20 nm-node planer MONOS NAND Flash memory is developed for the first time. Excellent performances such as fast program speed are realized without using FinFET structure. Furthermore, potential of tight Vth distribution is confirmed using 50 nm-node cells. These properties indicate that planer MONOS cell technology developed in this work can be one of candidates for multi-level NAND Flash memory with 20 nm-node and beyond.
VLSI Technology, 2009 Symposium on; 07/2009
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ABSTRACT: To recover visual sensation of blind patients, we have fabricated a fully implantable retinal prosthesis chip that includes photodetector and stimulus current generator. For the first time, we successfully implanted the retinal prosthesis chip bonded on the flexible cable with stimulus electrode array into a rabbit eyeball. Moreover, we recorded and analyzed electrically evoked potential (EEP) elicited from a rabbit brain by current stimulation to retina.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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M. Takayanagi, T. Watanabe,
R. Iijima,
M. Koyama,
M. Koike,
T. Ino,
Y. Kamimuta,
K. Sekine,
K. Eguchi,
A. Nishiyama,
K. Ishimaru
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ABSTRACT: Impact of implementation of HfSiON as a gate dielectric on sub-100 nm generation CMOSFET is reviewed. It is revealed that most parameters are affected when HfSiON with high Hf concentration is used, and thus, careful re-engineering is indispensable. We demonstrate HfSiON-CMOSFET for hp 65 nm LSTP application which meets the specification of ITRS roadmap by an adequate re-engineering
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S<sub>vg</sub> with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S<sub>vg</sub>) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 × 10<sup>17</sup> cm<sup>-3</sup>eV<sup>-1</sup>. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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A. Mineji,
Y. Tamura, T. Watanabe,
H. Ozaki,
F. Ootsuka,
T. Aoyama,
K. Shibata,
K. Tsujita,
N. Ohashi,
M. Yasuhira,
T. Arikado
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ABSTRACT: This paper describes the 65nm-node HfSiON transistors that have been fully integrated to SRAM array. By optimizing the thermal process after the gate stack formation, the scaling of EOT has been attained without introducing additional high-k formation techniques. Highly manufacturable HfSiON transistors with the symmetrical Vth values suitable for SRAM operation at 1.1V power supply are demonstrated.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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ABSTRACT: 65 nm gate length HfSiON-CMOSFET was fabricated with various Hf concentrations and gate spacers in view of device performance and reliability. The negative charges are generated in HfSiON/Si-substrate interface at the gate edge region for HfSiON with high Hf concentration. SiN offset spacer suppresses the charge generation and the degradation of drive current. Even so, HfSiON with low Hf concentration is higher at performance and reliability than that with high one. Moreover, the optimized HfSiON shows scalability of up to hp45 nm low standby power (LSTP).
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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N. Yasutake,
K. Ohuchi,
M. Fujiwara,
K. Adachi,
A. Hokazono,
K. Kojima,
N. Aoki,
H. Suto, T. Watanabe,
T. Morooka, [......],
M. Ohmura,
K. Miyano,
H. Yamada,
H. Tomita,
D. Matsushita,
K. Muraoka,
S. Inaba,
M. Takayanagi,
K. Ishimaru,
H. Ishiuchi
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ABSTRACT: High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V<sub>dd</sub> condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f<sub>i</sub> is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: This paper reports the hot carrier reliability of n-MISFET with HfSiON gate dielectrics and n<sup>+</sup> polysilicon gate electrode. It is found that generation of electron traps is the main cause of device degradation. The worst hot carrier stress condition is found to be V<sub>d</sub>=V<sub>g</sub> condition rather than the well-known condition of V<sub>g</sub> giving maximum substrate current (I<sub>sub</sub><sup>max</sup>), which is the worst condition for n-MOSFET with conventional SiO<sub>2</sub>. It is revealed that this difference originates from the difference in degradation mechanism.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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ABSTRACT: In this paper, we review our results on HfSiON deposited by MOCVD. Characteristics of capacitors and FETs fabricated by the conventional poly-Si gate CMOS process are discussed. We cover the issues of flatband voltage shift, effective inversion-layer mobility in relation to fabrication method of HfSiON, design consideration of HfSiON for 50 nm CMOSFETs and dielectric reliability.
Gate Insulator, 2003. IWGI 2003. Extended Abstracts of International Workshop on; 12/2003
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ABSTRACT: Characteristics of sub-100 nm CMOSFETs with HfSiON gate dielectrics with various Hf concentrations (𝒞;<sub>Hf</sub>) have been investigated, and the design guideline to obtain the superior device performance is presented for the first time. It is found that MOSFETs with lower 𝒞;<sub>Hf</sub> results in higher drive current due to lower parasitic resistance (R<sub>para</sub>) for the same effective oxide thickness (EOT). Therefore, 𝒞;<sub>Hf</sub> should be kept low in so far as it meets the ℐ;<sub>g</sub> target in order to obtain good MOSFET performance. It is demonstrated that 50 nm gate CMOSFETs with optimized HfSiON show high drive current of 650 μA/μm and 250 μA/μm for n-and p-MOSFET, respectively, with low gate leakage current (ℐ;<sub>g</sub>) of 0.3 A/cm<sup>2</sup> while maintaining the thermal stability up to 1050°C. This performance exceeds reported value of sub-100 nm CMOSFET with high-k materials.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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S. Inumiya,
K. Sekine,
S. Niwa,
A. Kaneko,
M. Sato, T. Watanabe,
H. Fukui,
Y. Kamata,
M. Koyama,
A. Nishiyama,
M. Takayanagi,
K. Eguchi,
Y. Tsunashima
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ABSTRACT: Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVD Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm<sup>2</sup>/Vs@0.8 MV/cm (85% of SiO<sub>2</sub>) and hole mobility of 73 cm<sup>2</sup>/Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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A. Hokazono,
K. Ohuchi,
M. Takayanagi,
Y. Watanabe,
S. Magoshi,
Y. Kato,
T. Shimizu,
S. Mori,
H. Oguma,
T. Sasaki,
H. Yoshimura,
K. Miyano,
N. Yasutake,
H. Suto,
K. Adachi,
H. Fukui, T. Watanabe,
N. Tamaoki,
Y. Toyoshima,
H. Ishiuchi
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ABSTRACT: High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
