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ABSTRACT: Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLKtrade) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Omega at 0.28 mumOslash with keeping large tolerance of misalignment up to 0.1 mum.
IEEE Transactions on Semiconductor Manufacturing 06/2008; · 0.72 Impact Factor
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S. Chikaki, K. Kinoshita,
T. Nakayama,
K. Kohmura,
H. Tanaka,
M. Hirakawa,
E. Soda,
Y. Seino,
N. Hata, T. Kikkawa,
S. Saito
[show abstract]
[hide abstract]
ABSTRACT: Feasibility for 32 nm node interconnect is depended on porous dielectric process technology. Self-assembled porous silica as a recent highest porosity material (50%) was successfully introduced into 200 nm pitch low-k/Cu damascene. The key technologies obtained in this work were novel rapid silylation hardening process with low temperature adsorption followed by rapid annealing, and reliable pore management at trench sidewall to introduce highly porous material to the low-k/Cu integration process. Performances of these technologies were confirmed to be extendible to 32 nm node, 100 nm pitch interconnects.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: Plasma-induced damages of porous silica films during plasma processes were investigated by using a plasma beam irradiation apparatus. We used the porous silica films incorporated with methyl groups to achieve high hydrophobicity. The carbon (methyl group) reductions in the film as an index of the level of damages induced by Ar, He, O2, H2, and N2 plasma irradiations were examined by x-ray photoelectron spectroscopy and secondary ion mass spectroscopy. The damage due to Ar and He plasma bombardment increased with an increase in the ion dosage, although it was not strongly affected by the ion energy in the range higher than 130 eV. Furthermore, it was found that the damage near the film surface was influenced more by metastable He atoms than by metastable Ar atoms. Both O ions and O atoms caused severe damage. N atoms did not affect the decrease of carbon content but reacted with carbon to form CN bonds. H atoms decreased carbon content slightly, but the amount of decrease was saturated by the further irradiation of H atoms.
Journal of Applied Physics 06/2007; 101(11):113301-113301-6. · 2.17 Impact Factor
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ABSTRACT: This paper describes the effects of recovery processes for the degradation caused by chemical mechanical polishing (CMP) in
the integration of Cu/porous silica low-
material interconnects
, in which
is used as CMP-Cap film (Cap-
) for
film. The leakage current and capacitance between Cu damascene interconnects increased when Cap-
was removed by CMP and the
was exposed, because the surfactant in CMP chemicals penetrated the
and the hydrophobicity of the
decreased, resulting in the increase of water absorption in the
. As a result of the recovery process after CMP, the leakage current has decreased by three orders of magnitude by applying
an isopropyl alcohol rinse and 1,3,5,7-tetramethyl-cyclo-tetrasiloxane (TMCTS) gas treatment, and the capacitance has decreased by 15% by applying the TMCTS gas treatment.
Journal of The Electrochemical Society. 04/2007; 154(5):H400-H405.
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T. Kikkawa,
S. Chikaki,
R. Yagi,
M. Shimoyama,
Y. Shishida,
N. Fujii,
K. Kohmura,
H. Tanaka,
T. Nakayama,
S. Hishiya,
T. Ono,
T. Yamanishi,
A. Ishikawa,
H. Matsuo,
Y. Seino,
N. Hata,
T. Yoshino,
S. Takada,
J. Kawahara,
K. Kinoshita
[show abstract]
[hide abstract]
ABSTRACT: An advanced scalable Cu damascene process was developed using self-assembled porous silica with tetramethylcyclo-tetrasiloxane (TMCTS) treatment and selective electroless plating of Cu barrier. It is found that the TMCTS vapor treatment could recover process-induced damages after plasma ashing and chemical mechanical polishing, resulting in no line-width dependence of the effective dielectric constant of the porous silica films. Furthermore, the selective electroplating of CoWP on Cu interconnects could suppress Cu drift and improve time-dependent dielectric breakdown of the porous silica film
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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S. Chikaki,
M. Shimoyama,
R. Yagi,
T. Yoshino,
Y. Shishida,
T. Ono,
A. Ishikawa,
N. Fujii,
T. Nakayama,
K. Kohmura,
H. Tanaka,
J. Kawahara,
H. Matsuo,
S. Takada,
T. Yamanishi,
S. Hishiya,
N. Hata,
K. Kinoshita, T. Kikkawa
[show abstract]
[hide abstract]
ABSTRACT: This paper describes the extraction of process-induced damage in low-k/Cu damascene by comparing measured data of interline capacitances of Cu interconnects and parasitic capacitances between the line and the substrate with simulation results. The effective dielectric constants were extracted by fitting the simulated results to the measured capacitances. The extracted dielectric constant of the low-k film increased from 2.1 to 4.5 with decreasing the spacing from 800 nm to 140 nm, indicating that the interfacial damage was induced between low-k and cap layer. It is shown that the interfacial damaged layer with a thickness of 10 nm and a k-value of 34.5 could be formed due to wet chemicals during CMP or Cu electrochemical plating or wet cleaning. The simulated interlines capacitance fitted well to measured data, assuming the void-like damage in the low-k film. Lateral sidewall damage could be caused by dry etching and ashing.
Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on; 10/2005
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M. Tada,
H. Ohtake,
M. Narihiro,
F. Ito,
T. Taiji,
M. Tohara,
K. Motoyama,
Y. Kasama,
M. Tagami,
M. Abe, [......],
T. Onodera,
J. Kawahara,
K. Kinoshita,
N. Hata, T. Kikkawa,
Y. Tsuchiya,
K. Fujii,
N. Oda,
M. Sekine,
Y. Hayashi
[show abstract]
[hide abstract]
ABSTRACT: Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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R. Yagi,
S. Chikaki,
M. Shimoyama,
T. Yoshino,
T. Ono,
A. Ishikawa,
N. Fujii,
N. Hata,
T. Nakayama,
K. Kohmura,
H. Tanaka,
T. Goto,
J. Kawahara,
Y. Sonoda,
H. Matsuo,
Y. Seino,
K. Kinoshita, T. Kikkawa
[show abstract]
[hide abstract]
ABSTRACT: New methods to recover process-induced damages of a self-assembled non-periodic porous silica (k=2.1) film were developed for Cu/low-k damascene interconnects for 45nm technology node and beyond. It is shown that process-induced damages can be suppressed by employing 1,3,5,7-tetra-methylcyclotetrasiloxane (TMCTS) vapor annealing after dry etching, by using a new suppressor for a Cu plating solution, and by post Cu-CMP cleaning with ethanol. Time-dependent dielectric breakdown lifetime of the non-periodic porous silica/Cu damascene was evaluated to be more than 10 years.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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S. Chikaki,
A. Shimoyama,
R. Yagi,
T. Yoshino,
T. Ono,
A. Ishikawa,
N. Fujii,
N. Hata,
T. Nakayama,
K. Kohmura, [......],
Y. Sonoda,
H. Matsuo,
Y. Seino,
S. Takada,
N. Kunimi,
Y. Uchida,
S. Hishiya,
Y. Shishida,
K. Kinoshita, T. Kikkawa
[show abstract]
[hide abstract]
ABSTRACT: Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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[show abstract]
[hide abstract]
ABSTRACT: It is demonstrated that dry etching and ashing damage in porous silica low-k films is recovered by TMCTS (1, 3, 5, 7-tetramethylcyclotetra-siloxane) vapor post annealing. The increase in k-value after Ar/C<sub>5</sub>F<sub>8</sub>/O<sub>2</sub> plasma etching was reduced from 35% to 6.5% of the initial value (k=2.25) by TMCTS annealing. The leakage current was also recovered to the original level. The HF wet etching revealed that the gas chemistries both with and without oxygen caused the sidewall damaged region in the porous silica trench and the TMCTS annealing was effective to recover the sidewall damage. Fourier transformed infrared absorption measurements indicated that the replacement of Si-CH<sub>3</sub> bonds in low-k films by Si-O and Si-OH bonds occurred during the plasma treatments. The recovery mechanism is that hydrophobic bonds (-CH<sub>3</sub>) were reintroduced into the film and a stable cross-linked poly(TMCTS) network was formed on the pore wall surfaces by the TMCTS post annealing.
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on; 06/2005
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T. Kikkawa,
Y. Oku,
K. Kohmura,
N. Fujii,
H. Tanaka,
T. Goto,
A. Ishikawa,
H. Matsuo,
H. Miyoshi,
A. Nakano,
Y. Sonoda,
N. Hata,
Y. Seino,
T. Yoshino,
S. Takada,
K. Kinoshita
[show abstract]
[hide abstract]
ABSTRACT: A novel ultra-low-k porous silica film was developed by use of a self-assembly technology. A periodic hexagonal porous silica film and disordered porous silica film were formed by self-assembling surfactants and acidic silica derived from tetraethoxysilane (TEOS) on a Si substrate. The properties of the periodic porous film such as porosity, pore diameter and resulting dielectric constant can be controlled by the alkyl chain length of the surfactant and the molecular ratio of surfactant/Si. The mechanical properties of the porous silica film can be reinforced by introducing tetramethyl-cyclo-tetra-siloxane (TMCTS) treatment without increasing the dielectric constant. The elastic modulus of 8 GPa and dielectric constant of 2 were achieved for the porous silica film. Ultra-low-k/Cu damascene integration was demonstrated for 45 nm BEOL technology.
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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[show abstract]
[hide abstract]
ABSTRACT: We have demonstrated that the mechanical strength of organic silica low-k films can be enhanced by introducing a reinforcement monomer in a matrix monomer under plasma excitation. The modulus improvement mechanism was investigated by analyzing the film structure. Pyrolysis gas chromatography / mass spectrometry (Py-GC/MS) revealed incorporation of a reinforcement monomer in the matrix through co-polymerization reactions. Compositional analysis of the films showed that the extent of reinforcement is associated with co-polymerization ratio or the monomer content in the film. It is also indicated that the modulus enhancement depends on the content of 3D aromatic bridge structure, which is affected by the chemical structure of the reinforcement monomers.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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Y. Oku,
K. Yamada,
T. Goto,
Y. Seino,
A. Ishikawa,
T. Ogatal,
K. Kohmura,
N. Fujii,
N. Hata,
R. Ichikawa, [......],
C. Negoro,
A. Nakano,
Y. Sonoda,
S. Takada,
H. Miyoshi,
S. Oike,
H. Tanaka,
H. Matsuo,
K. Kinoshita, T. Kikkawa
[show abstract]
[hide abstract]
ABSTRACT: Novel ultra-low-k porous silica films were developed by use of a self-assembly technology. The mechanical properties of the porous silica films could be reinforced independently of the dielectric constant by introducing a tetramethyl-cyclo-tetra-siloxane (TMCTS) treatment. High modulus porous silica films, with an elastic modulus of 8 GPa and dielectric constant of 2, can be achieved simultaneously. Ultra-low-k/Cu damascene with sufficient mechanical strength was demonstrated for 45 nm BEOL (back-end-of-line) technology.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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J. Kawahara,
A. Nakano,
N. Kunimi,
K. Kinoshita,
Y. Hayashi,
A. Ishikawa,
Y. Seino,
T. Ogata,
H. Takahashi,
Y. Sonoda,
T. Yoshino,
T. Goto,
S. Takada,
R. Ichikawa,
H. Miyoshi,
H. Matsuo,
S. Adachi, T. Kikkawa
[show abstract]
[hide abstract]
ABSTRACT: A new plasma-enhanced co-polymerization (PCP) technology is developed for low-k/Cu damascene integration on 300 mm wafers. The concept of the PCP technology is to introduce monomers, which have different functions such as matrix formation, deposition acceleration, or reinforcement, into a reactor exited with a He-plasma. It is shown that the low-k film growth rate from the matrix monomer such as divinyl siloxane-benzocyclobutene (DVS-BCB) and the elastic modulus of the deposited films are enhanced by adding a deposition acceleration monomer and a reinforcement monomer, respectively, without increasing the k-value. Combining the PCP technology with an ultra-low-pressure CMP technique, the Cu damascene interconnects were successfully fabricated on 300 mm wafers.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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[show abstract]
[hide abstract]
ABSTRACT: We have demonstrated that the periodicity in pore structure increases the elastic modulus E with maintaining the dielectric constant k by analytical and numerical calculations. The periodic porous silica films having the hexagonal arrangement of circular cylindrical pores with k<2.0 and E>3 GPa is feasible at the porosity of 0.62 with the bulk material of k<sub>b</sub>=4.0 and E<sub>b</sub>>21 GPa. Calculation results have been confirmed with the experimental data by taking into account the experimental pore shape. The periodic porous silica films having the three-dimensional cubic structure of spherical pores with k<2.0 and E>3GPa is feasible at the porosity of 0.60 using the bulk material of k<sub>b</sub>=4.0 and E<sub>b</sub>>12 GPa.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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[show abstract]
[hide abstract]
ABSTRACT: The need of introducing higher density of nanopores into interlayer dielectrics to realize k<2.0 increases the danger of pore coagulation to form unexpectedly large 'killer' pores, which cause defects in Cu diffusion barrier layer to lead to device failure. On the other hand, unintentional small micropores with less than 0.7 nm in diameter are also problematic in terms of physico-chemical and mechanical stability. In this work, we employ two different low-k films with k=1.8 and show experimental results on the largeand small-ends of pore size distributions to address most important technological issues in ultra-low-k/Cu interconnects.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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[show abstract]
[hide abstract]
ABSTRACT: We propose and demonstrate experimentally a structural characterization technique for ultra-low-dielectric-constant thin films with periodic porous structures [1-3] by employing X-ray diffraction / scattering measurements. The analytical approach that we propose here takes into account specular reflection, incoherent scattering from random distribution of electron density, and coherent scattering from periodically modulated distribution of electron density. From the analysis, inter-pore distances and pore diameters in the directions perpendicular and parallel to the film surface are determined with which the film porosity is calculated. Thus obtained porosity is then used to discuss the film density and dielectric constant in comparison to those of non-porous reference sample.
MRS Proceedings. 12/2001; 716.
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[show abstract]
[hide abstract]
ABSTRACT: A new cobalt (Co) salicide technology for sub-quarter micron CMOS
transistors has been developed using high-temperature sputtering and in
situ vacuum annealing. Sheet resistance of 11 Ω/□ for both
gate electrode and diffusion layer was obtained with 5-nm-thick Co film.
No line width dependence of sheet resistance was observed down to
0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The
high temperature sputtering process led to the growth of epitaxial CoSi
<sub>2</sub> layers with high thermal stability. By using this
technology 0.15 μm CMOS devices which have shallow junctions were
successfully fabricated
IEEE Transactions on Electron Devices 12/1998; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: A fully-dry cleaning technique with Ar/H<sub>2</sub> Electron
Cyclotron Resonance (ECR) plasma was developed as a low contact
resistance metallization technology for gigabit scale DRAM contacts. By
combining with ECR TiN/Ti-CVD, extremely low contact resistances of 296
Ω and 350 Ω for 0.3-μm contact diameter with aspect ratio
of 7 were realized on n<sup>+</sup> and p<sup>+</sup> diffusion layers,
respectively. No leakage current was observed. By using this technology,
a DRAM ULSI, which was planarized by Chemical Mechanical Polishing (CMP)
and had deep contact holes with aspect ratio of 6, was successfully
demonstrated
IEEE Transactions on Electron Devices 05/1997; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: A new titanium-tungsten (Ti-W) salicide process with high-thermal stability has been developed for deep-submicron logic with embedded DRAM. The sheet resistance of 14 Ω/□ for Ti-5at%W silicide on both 0.18 μm gate and 0.35 μm diffusion layers was achieved. This is the lowest resistivity (50 μΩ-cm) in C49-TiSi<sub> 2</sub>, and did not change during annealing at 800°C for 1 hour. By adding W atoms in Ti, high-thermal stability of the metastable C49-TiSi<sub> 2</sub> was obtained, so that the C49-TiSi<sub> 2</sub> did not transform to the C54-TiSi<sub> 2</sub> phase below 900°C. 0.18 μm CMOS transistors were successfully fabricated using the Ti-W salicide technology.
Electron Devices Meeting, 1996., International; 01/1997
