T Meguro

Publications (4)4.59 Total impact

• Source

  Available from: arxiv.org

  Article: Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers

  J. Hayakawa, S. Ikeda, K. Miura, M. Yamanouchi, Young Min Lee, R. Sasaki, M. Ichimura, K. Ito, T. Kawahara, R. Takemura, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, H. Ohno
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  ABSTRACT: We investigated the effect of using a synthetic ferrimagnetic (SyF) free layer in MgO-based magnetic tunnel junctions (MTJs) on current-induced magnetization switching (CIMS), particularly for application to spin-transfer torque random access memory (SPRAM). The employed SyF free layer had a Co₄₀Fe₄₀B₂₀/Ru/Co₄₀Fe₄₀B₂₀and Co₂₀Fe₆₀B₂₀/Ru/Co₂₀Fe₆₀B₂₀structures, and the MTJs (100 times (150-300) nm²) were annealed at 300 ^degC. The use of SyF free layer resulted in low intrinsic critical current density ( J _c0) without degrading the thermal-stability factor ( E / k _B T , where E , k _B, and T are the energy potential, the Boltzmann constant, and temperature, respectively). When the two CoFeB layers of a strongly antiferromagnetically coupled SyF free layer had the same thickness, J _c0 was reduced to 2-4 times10⁶ A/cm². This low J _c0 may be due to the decreased effective volume under the large spin accumulation at the CoFeB/Ru. The E / k _B T was over 60, resulting in a retention time of over ten years and suppression of the write current dispersion for SPRAM. The use of the SyF free layer also resulted in a bistable (parallel/antiparallel) magnetization configuration at zero field, enabling the realization of CIMS without the need to apply external fields to compensate for the offset field.
  IEEE Transactions on Magnetics 08/2008; · 1.36 Impact Factor
• Article: 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

  T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, Young Min Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, H. Ohno
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  ABSTRACT: A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.
  IEEE Journal of Solid-State Circuits 02/2008; · 3.23 Impact Factor
• Conference Proceeding: Current-driven magnetization switching in CoFeB/MgO/CoFeB magnetic tunnel junctions

  J Hayakawa, S Ikeda, Y Lee, R Sasaki, F. Matsukura, T Meguro, H Takahashi, H Ohno
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  ABSTRACT: The current-driven magnetization switching in CoFeB/MgO/CoFeB magnetic tunnel junctions (MTJs) with various free layer materials including synthetic structure was studied in this paper. The MTJ films were deposited on SiO₂/Si substrates using RF magnetron sputtering. The tunnel magnetoresistance (TMR) ratios and current-voltage (I-V) characteristics of the the MTJs were measured at room temperature using a dc four-probe method and with a magnetic field of up to 1 kOe. The TMR ratio and the current-driven magnetization switching at critical current densities were shown as a function of annealing temperature for two types of MTJs with different free layer.
  Magnetics Conference, 2006. INTERMAG 2006. IEEE International; 06/2006
• Conference Proceeding: 2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching

  R. Takemura, T. Kawahara, K. Miura, J. Hayakawa, S. Ikeda, Y.M. Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, H. Ohno
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  ABSTRACT: A 1.8 V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2-mum logic process with MgO tunneling barrier cell demonstrates the circuit technologies for potential low power non-volatile RAM, or universal memory. This chip features: an array scheme with bit-by-bit bi-directional current write to achieve proper spin-transfer torque writing of 100-ns, and parallelizing-direction current reading with low voltage bit-line that leads to 40-ns access time.
  Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on;