T. Lutz

Infineon Technologies, München, Bavaria, Germany

Are you T. Lutz?

Claim your profile

Publications (12)10.37 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Electron beam direct write (EBDW) provides high resolution for device and technology development. A new variable shaped beam system with improved electron optics was introduced, which features the capability for the 32nm node. Because of the limited resolution of commercially available chemically amplified resists at this node, it is important to determine a stable and optimum resist process window. To compare a process window under different premises, a universally applicable and low error-prone method is needed. The isofocal dose method is investigated with regard to these properties for its use in EBDW. Experiments were performed on 50kV variable shaped electron beam direct writers using the new electron-optical column SB3050 DW (Vistec Electron Beam GmbH). Exposures are performed at different sites in Dresden (Fraunhofer CNT/Qimonda Dresden), Jena (Vistec) and Stuttgart (IMS Chips); also patterns are exposed on different layer stacks at one site. The strong need for a process window can be fulfilled by the isofocal dose method, which will be shown by contour plots.
    Microelectronic Engineering 05/2008; 85(5):778-781. DOI:10.1016/j.mee.2008.01.042 · 1.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Electron beam direct write (EBDW) with a variable shaped beam writer can be applied for very low volume applications like prototyping and personalization. Together with Infineon Technologies, the Center of Competence E-Beam Lithography of Qimonda in Dresden has demonstrated the integration of an E-Beam written back end of line metal layer into a productive 220 nm node microcontroller fabrication process. For this purpose an electron beam lithography unit process was developed, and all necessary steps like data prep, proximity correction, alignment and overlay processes and etching processes were reviewed. Several test wafers have been completed in fabrication and measured electrically. At first go, full electrical functionality with a yield >70% could be demonstrated.
    Microelectronic Engineering 05/2008; 85(s 5–6):792–795. DOI:10.1016/j.mee.2007.12.055 · 1.20 Impact Factor
  • C. Hohle · C. Arndt · K.-H. Choi · J. Kretz · T. Lutz · F. Thrum · K. Keil ·
    [Show abstract] [Hide abstract]
    ABSTRACT: An overview about process window evaluation and characteristic features of photoresists for e-beam/optical hybrid lithography as well as mix and match applications and implementation into new integration concepts is given. For that, several commercially available deep ultraviolet (DUV) (248 nm), ArF (193 nm), and e-beam resist samples from various suppliers were exposed at Qimonda’s dynamic random access memory pilot line environment using both e-beam and optical exposure. Due to the diverse, sometimes contradictory requirements and properties of the different material platforms (e.g., resolution, sensitivity, vacuum stability, etch resistance, etc.), a unique material for true hybrid lithography is difficult to find. At least the tested DUV resist is limited applicable for e-beam exposures putting up with low e-beam sensitivity.
    Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures 11/2007; 25(6). DOI:10.1116/1.2779043 · 1.36 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Flash memory cells based on a silicon nitride charge trapping layer and multi-gate layout with gate lengths smaller than 48nm have been investigated as a suitable successor to state-of-the-art non-volatile floating gate memory cells. The NAND memory arrays based on SONOS (silicon-oxide–nitride-oxide–silicon) fin-FET transistors were fabricated using e-beam lithography and hydrogen-silsesquioxane (HSQ) resist. The lithographic procedures to compensate for the topography, positioning, resolution and proximity issues are presented together with electrical characterization. Double fin active areas were structured on top of an optically pre-structured SOI-wafer using an HSQ resist coated in a single step. After etching the silicon fins, an ONO (oxide–nitride-oxide) stack as well as a poly-silicon gate electrode layer were deposited. The structuring of these layers with high topography was accomplished by exposing a double coated HSQ resist film. The first, bottom resist layer acts as planarization layer to obtain a flat surface for the second coating step. After structuring the gate using this resist stack, the device mini-array is completed by a single layer metallization.
    Microelectronic Engineering 05/2007; 84(5):1578-1580. DOI:10.1016/j.mee.2007.01.255 · 1.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: When using electron beam direct write for patterning, resist selection (positive or negative) plays an important role. This is because writing time for shaped beam machines is proportional to the mean density of exposed shapes. There is an optimum with respect to writing time when using either the direct exposure or the complementary exposure with reversed resist tonality. Switching from positive to negative resist or vice versa has an impact on writing time. In this paper, we derive the fundamental differences on CD accuracy when using direct or complementary exposure, which is given by the local registration error. Additionally, a simple method is developed to measure this local registration error by simple CD SEM measurement of 1:1 line/space patterns.
    Microelectronic Engineering 05/2007; 84(5):1033-1036. DOI:10.1016/j.mee.2007.01.141 · 1.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: For Electron Beam Direct Write (EBDW) a systematic investigation of defect density using a Negevtech 3100 darkfield inspection system was performed. A special defect learning pattern for memory applications with coverage of 50% was designed and printed partially on 300mm wafers using chemically amplified positive and negative E-Beam resists. By optical defect measurements post litho it was possible to inspect 50nm dense lines to characterize the exposure system as well as the used resist process. Using this method a large exposed area in millimeter range can be inspected and an overview on exposure quality can be gained in a reasonable amount of time. Particle measurements were performed additionally to distinguish between particles and exposure issues. By using darkfield measurements, process related issues like development problems and resist residuals can be found, as well as writing issues like shot butting and write field stitching can be quickly determined and controlled with this method. In this paper, the measurement methodology is described as well as the effect of writer imperfections on the darkfield images. A pareto analysis is performed and shows the frequency of occurrence of different defects. Measures to reduce defects - especially on the tool side - are given. The method is feasible to use in a regular check to control tool and process performance.
    Proceedings of SPIE - The International Society for Optical Engineering 03/2007; DOI:10.1117/12.712078 · 0.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: If electron beam technology is used for direct writing on Si wafers (synonym EBDW) there have to be taken into account a number of specific issues concerning the layout data preparation differing considerably from those of mask writing. This is especially true because EBDW enables the most advanced technology levels which are in general one or two nodes ahead of the mainstream optical lithography. Consequently we will have to face up to additional challenges, such like high resolution and the corresponding CD¿control parameters. In order to achieve acceptable turn around times the shaped beam writers have proven to be the tool of choice. To demonstrate this behind a practical background we describe our experiences collected during 300mm wafer exposures with a SB351/3050 tool installed at the Fraunhofer Center Nanoelectronic Technology (CNT) in Dresden/Germany. Appropriate solutions are presented showing how to execute such procedures like layout fracturing and Proximity Effect Correction (PEC) of high-density layouts on a Linux computing cluster. The CD accuracy of lines being of particular interest in connection with sub 50 nm patterns being analyzed and a new model-based method allowing the reduction of the before mentioned effect is evaluated. In any case, whether it is about short or time-consuming exposures, a precise forecast of the total processing time of the wafer in the e-beam exposure tool is of great importance. Practical findings from the use of a simulation tool specifically developed for this purpose are discussed in this paper.
    Mask and Lithography Conference (EMLC), 2007 23rd European; 02/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaV<sub>th</sub> = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work characterizes long channel trigate transistors with respect to the systematic influence of crystal orientation and body doping on performance issues like mobility and Vth adjustment. A fin orientation of 〈1 0 0〉 is found favourable for n-channel, 〈1 1 0〉 for p-channel transistors. Experiment shows that body doping is suitable to taylor Vth, but low doping levels are preferable to reduce Vth variations. The applicability of these long channel results to short-channel transistors down to 20 nm gate length is demonstrated and good performance is obtained.
    Solid-State Electronics 01/2006; 50(1-50):38-43. DOI:10.1016/j.sse.2005.10.041 · 1.50 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The trimming of electron beam features is investigated to explore the limits of this scaling technique for the fabrication of nano-scale devices. The semiconductor industry, in particular, needs features below 50 nm, e.g., for extremely small gates for future technology nodes. In addition, sub-lithographic structures are required for other device concepts, such as the fin-type field effect transistor (FinFET). The trimming of very thin layers of calixarene, an organic resist material, as well as an oxide-like resist (hydrogen-silesquioxane) were investigated and extremely small feature sizes, well below 10 nm, were achieved. Resist structures down to 4 nm in width and silicon features of about 8 nm have been successfully fabricated. Different trimming procedures utilizing plasma resist trimming, etching of Tetraethylorthosilicate (TEOS) hard-masks in hydrofluoric acid (HF) and sacrificial oxidation were compared and, for the first time, a comprehensive study of these techniques applied to sub-10 nm-structuring is presented. In summary, results prove the potential of the trimming procedures investigated here, each of which has specific applications.
    Microprocesses and Nanotechnology Conference, 2005 International; 11/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A novel fabrication concept, Epi-Before-Bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentally shown that specific off-current requirements can be fulfilled with conventional poly-Si gates.
    SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
  • J. Kretz · L. Dreeskornfeld · G. Ilicali · T. Lutz · W. Weber ·
    [Show abstract] [Hide abstract]
    ABSTRACT: For the fabrication of future MOSFET device demonstrators with electron beam lithography negative resists with target resolutions smaller than 20 nm are needed. Calixarenes and hydrogen-silesquioxane are commonly used resists at present for this critical dimension (CD). We have compared two organic calixarene derivatives, 4-methyl-acetoxy-calix-6-arene and chloro-methyl-tetrakis-methoxy-calix-4-arene and the inorganic low-k material hydrogen-silesquioxane in terms of their compatibility to standard CMOS processes. Resist thicknesses of 50–150 nm have been produced with both types of resist with different dilutions. Contrasts are 1.8 for both calixarenes, with a clearing dose of 1200 μC/cm2 for calix-6-arene and 330 μC/cm2 for calix-4-arene. The contrast of 2.3 at 67 μC/cm2 for HSQ could be increased to 3.3 by use of Choline developer instead of TMAH. Dose dependence on linewidth has been studied in detail. Etching selectivities of 4:1 for calixarene to TEOS in a fluorine gas mixture and 14:1 of densified HSQ to Si in an HBr/O2 plasma have been achieved.
    Microelectronic Engineering 03/2005; 78(1):479-483. DOI:10.1016/j.mee.2004.12.061 · 1.20 Impact Factor