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ABSTRACT: The effects of reoxidation on the band structure of N-incorporated SiON films were investigated as a function of thermal treatment in NO and NH3. Reoxidation-associated changes in band gap and valence band offset of the N-incorporated SiON films prepared by sequential thermal annealing in both NO and NH3 were less than those observed for the nitrided film prepared by thermal annealing in only NH3. The differences in band-alignment characteristics of the nitrided films that resulted from use of different nitridation methods were strongly related to the depth distribution of N and the chemical states of N bonded to Si.
Applied Physics Letters 07/2008; 93(1):012901-012901-3. · 3.84 Impact Factor
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H.B. Lee,
J.W. Hong,
G.J. Seong,
J.M. Lee,
H. Park,
J.M. Baek,
K.I. Choi,
B.L. Park,
J.Y. Bae,
G.H. Choi,
S.T. Kim, U.I. Chung,
J.T. Moon,
J.H. Oh,
J.H. Son,
J.H. Jung,
S. Hah,
S.Y. Lee
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ABSTRACT: This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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ABSTRACT: This paper reports the reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. Hot carrier stress (HCS) at Isub, max condition on thick oxide is found to be the most critical part among the various reliability concerns. Regardless of gate dielectric and gate oxide thickness, the degradation behavior of the condition of Isub, max and Vg=Vd HCS is mainly SS increase and Vth shift, respectively. Therefore, for precise evaluation of the device reliability, it is necessary that HC immunity at Isub, max stress should be checked in thick oxide transistor below 50 nm design rule era.
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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ABSTRACT: This work focuses on magnetic tunnel junctions with a MgO barrier layer made by RF-sputtering and radical oxidation. In case of RF-sputtered MgO, its crystal orientation, MR and RA values very sensitively depend on the chamber atmosphere. The MR ratio of 97% in radical oxidized MgO is obtained at 0.4 V, which is slightly higher than RF-sputtered MgO. Also, its RA is smaller than that of RF-sputtered MgO. These improved MgO properties are originated from the improvement of the crystal orientation of MgO(200) and the decrease of OH component within the MgO barrier. In addition, the breakdown voltage in radical oxidized MgO is higher than that of RF-sputtered MgO at the same MgO thickness
IEEE Transactions on Magnetics 11/2006; · 1.36 Impact Factor
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ABSTRACT: Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×10<sup>10</sup>/cm<sup>2</sup>is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested.
Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on; 07/2006
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ABSTRACT: For the first time, we successfully developed highly reliable 50nm-thick polycrystalline PZT capacitor using noble Ir/SrRuO<sub>3</sub> top electrode and MOCVD PZT technology. In the 50nm-thick PZT capacitor, 33μC/cm<sup>2</sup> of remanent polarization and 0.7V of saturation voltage have been demonstrated. Moreover, after 100hrs of bake-time at 150°C, opposite-state polarization margin was over 23μC/cm<sup>2</sup>, which is world-wide best result so far achieved. Using this capacitor technology, highly reliable low voltage operating embedded FRAM device was successfully developed.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: The microstructure of Ta2O5 thin films, deposited onto Si substrates by atomic layer deposition (ALD), was investigated, using in situ transmission electron microscopy (TEM). As-deposited amorphous films crystallize as the orthorhombic phase L-Ta2O5 upon heating at 750°C. Two dominant crystallographic orientations are found, one with (0 0 1) and (1 11 0) planes perpendicular to the substrate, while the other has (0 0 1) planes parallel to the substrate. The grains consist of subgrains which are rotated a few degrees with respect to each other. The kinetics of the crystallization were studied by in-situ TEM heating experiments carried out at nominal temperatures of 790°C, 820°C and 850°C. They reveal that the growth and crystallization activation energies are about 4.2 eV and 6.3 eV, respectively. Tilted subgrains keep forming during growth until they come in contact with neighbouring grains. The crystallization behaviour can be approximated by the Kolmogorov–Johnson–Mehl–Avrami (KJMA or Avrami) equation, giving mode parameters of 2.5, 1.9, and 1.7 at 790°C, 820°C and 850°C, respectively. A small value of mode parameters is attributed to decreasing growth and nucleation rates with time.
Philosophical Magazine. 06/2005; 85(18):2049-2063.
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H.-J. Cho,
H.L. Lee,
S.G. Park,
H.B. Park,
T.S. Jeon,
B.J. Jin,
S.B. Kang,
S.G. Lee,
Y.P. Kim,
I.S. Jung,
J.W. Lee,
Y.G. Shin, U.-I. Chung,
J.T. Moon,
J.H. Choi,
Y.S. Jeong
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ABSTRACT: The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 μm and improved MOSFET characteristics.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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B. J. BAE,
J. E. LIM,
D. C. YOO,
S. D. NAM,
J. E. HEO,
D. H. IM,
B. O. CHO,
S. O. PARK,
H. S. KIM, U. I. CHUNG,
J. T. MOON
Integrated Ferroelectrics 01/2005; 75(No.):235-241. · 0.30 Impact Factor
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ABSTRACT: Dependence of magnetic tunnel junction (MTJ) properties on seed layer, surface treatment and magnetic materials was investigated to improve TMR ratio. Roughness of tunnel oxide layer generated from seed layer roughness reduces TMR ratio as well as RA product owing to locally reduced oxide layer thickness. Crystallinity of seed layer is found to be important to enhance TMR ratio. Surface treatment with ion beam etching on a pinned layer improves tunnel oxide uniformity providing higher TMR ratio. Also, highly polarized magnetic material increases TMR ratio but the effect of surface treatment is quite different depending on pinned layer material.
IEEE Transactions on Magnetics 08/2004; · 1.36 Impact Factor
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Y.K. Ha,
J.E. Lee,
H.-J. Kim,
J.S. Bae,
S.C. Oh,
K.T. Nam,
S.O. Park,
N.I. Lee,
H.K. Kang, U.-I. Chung,
J.T. Moon
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ABSTRACT: Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron penetration in DRAMs, which has higher thermal budget than other devices, and that the NCDM tool can be used for checking the degree of plasma nitridation. We assure that the NCDM tool is a time-effective tool for plasma nitridation process development.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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I.G. Baek,
J.E. Lee,
H.-J. Kim,
Y.K. Ha,
J.S. Bae,
S.C. Oh,
S.O. Park, U.-I. Chung,
N.I. Lee,
H.K. Kang,
J.T. Moon
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ABSTRACT: The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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ABSTRACT: A novel CVD-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVD-cobalt salicidation, identical values of low sheet resistance can be realized on actives and gates regardless of the surrounding geometry, due to its excellent conformality. In addition, a low contact resistance can be obtained in small metal/active contacts even with high post thermal budget when CVD-Co is applied as an ohmic layer due to its conformality and inertness with the dopants. CVD-cobalt is a needed and suitable solution for the salicidation and silicidation of not only the continuously scaling conventional CMOS, but also the emerging next generation of devices with complex shapes and structures such as vertical and 3D FET.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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T. Park,
S. Choi,
D.H. Lee,
J.R. Yoo,
B.C. Lee,
J.Y. Kim,
C.G. Lee,
K.K. Chi,
S.H. Hong,
S.J. Hynn,
Y.G. Shin,
J.N. Han,
I.S. Park, U.I. Chung,
J.T. Moon,
E. Yoon,
J.H. Lee
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ABSTRACT: Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I<sub>SUB</sub>/I<sub>D</sub> than planar type DRAM cell transistors.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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Y.N. Hwang,
J.S. Hong,
S.H. Lee,
S.J. Ahn,
G.T. Jeong,
G.H. Koh,
J.H. Oh,
H.J. Kim,
W.C. Jeong,
S.Y. Lee, [......],
Y.H. Ha,
J.H. Yi,
W.Y. Cho,
Y.T. Kim,
K.H. Lee,
S.H. Joo,
S.O. Park, U.I. Chung,
H.S. Jeong,
Kinam Kim
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ABSTRACT: We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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ABSTRACT: The characteristics of cell transistor with low energy junction implantation and recessed junction, which is formed by in_situ phosphorus doped selective silicon growth, are investigated. Adding the low energy n-junction implantation drastically reduces the contact resistance of pad/n-junction. And also, the drive current is improved without any degradation of BV (Breakdown Voltage) and leakage characteristics. Plasma damage free TDSE (Thermal Desorption of Silicon Etching) processing using the Cl<sub>2</sub> gas chemistry in UHV CVD Chamber is used to control the junction depth. The recessed junction is formed with phosphorus-doped silicon using the SEG (Selective Epitaxial Growth) process and the characteristics of recessed junction are evaluated.
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on; 10/2002
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S. Choi,
B.Y. Nam,
J.-H. Ku,
D.C. Kim,
S.H. Lee,
J.J. Lee,
J.W. Lee,
J.D. Ryu,
S.J. Heo,
J.K. Cho, [......],
C.J. Choi,
Y.J. Lee,
J.H. Chung,
B.H. Kim,
M.B. Lee,
G.H. Choi,
Y.S. Kim,
K. Fujihara, U.I. Chung,
J.T. Moon
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ABSTRACT: Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W<sub>x</sub>N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta<sub>2</sub>O<sub>5</sub>/poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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K. M. Lee,
K. S. Park,
S. D. Nam,
S. W. Lee,
S. H. Joo,
J. S. Seo,
Y. D. Kim,
S. L. Cho,
Y. H. Son,
H. G. An,
H. J. Kim,
Y. J. Chung,
J. E. Heo,
M. S. Lee,
S. O. Park, U. I. Chung,
J. T. Moon
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ABSTRACT: Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550°C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.
Integrated Ferroelectrics 01/2002; 48(1):171-180. · 0.30 Impact Factor
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Seungheon Song,
W.S. Kim,
J.S. Lee,
T.H. Choe,
J.H. Choi,
M.S. Kang, U.I. Chung,
N.I. Lee,
K. Fujihara,
H.K. Kang,
S.I. Lee,
M.Y. Lee
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ABSTRACT: Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below
2.0 nm were fabricated and characterized. Super-steep retrograde channel
profiles using boron (NMOS) or arsenic (PMOS) channel implantation
followed by selective epitaxial growth of undoped-Si were found to
effectively reduce short-channel effect and improve current drivability
even in the sub-100 nm regime. For NMOS, indium implanted devices showed
better short-channel immunity, however, no improvement in current
drivability was observed. Optimization of the gate oxide thickness
versus gate length was investigated in the presence of direct tunneling
leakages and for the first time, an experimental guideline of oxide
scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm
stack gate dielectrics of oxynitride and LPCVD nitride were developed,
which showed excellent transistor characteristics
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
