T.P. Chow

Publications (38)46.38 Total impact

• Conference Proceeding: Application of GaAs pHEMT technology for efficient high-frequency switching regulators

  V. Pala, H. Peng, M. Hella, T.P. Chow
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  ABSTRACT: The potential of GaAs pHEMT technology for low-voltage high-frequency power switching applications is discussed with a view towards their application for power supplies in portable electronic systems. The design and implementation of a 4.5V-to-3.3V buck converter power IC utilizing an enhancement mode pHEMT high side switch is demonstrated. The fabricated buck circuit is capable of operating at switching frequencies ranging from 100-MHz. While operating from a 4.5V supply a power efficiency of 87% is obtained at 100MHz when the output voltage is 3.3V and current is 500mA.
  Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on; 07/2010
• Source

  Available from: rpi.edu

  Conference Proceeding: A 150MHz, 84% efficiency, two phase interleaved DC-DC converter in AlGaAs/GaAs P-HEMT technology for integrated power amplifier modules

  Han Peng, V. Pala, T.P. Chow, M. Hella
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  ABSTRACT: This paper presents a high efficiency, high switching speed, two-stage interleaved DC-DC buck converter with negatively-coupled inductors in AlGaAs/GaAs technology, targeting integrated power amplifier modules. The flip chip DC-DC converter is implemented in 0.5 μm GaAs pHEMT process and occupies 2 × 2.1mm² without the output network. The inductors in the output network are implemented in 65 μm thick top copper metal layer and have a quality factor of 25 at 150 MHz. The interleaved DC-DC converter achieves 84% efficiency when operating at 150MHz switching frequency with 4.5V/3.3V conversion ratio and 1A load current.
  Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
• Article: Design and simulations of novel enhancement‐mode high‐voltage GaN vertical hybrid MOS‐HEMTs

  Z. Li, K. Tang, T. P. Chow, M. Sugimoto, T. Uesugi, T. Kachi
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  ABSTRACT: The design, simulations and optimization of a novel high-voltage vertical GaN MOS-controlled High Electron Mobility Transistor (HEMT) with epitaxially grown thin p type body and terrace gate structure is presented, with projected maximum breakdown voltage of 1289 V, Ron,sp of 1.9 mΩ-cm2, and switching power loss of 34.9 μJ/cm2 and 2.60 μJ/cm2 for drain and gate respectively. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
  physica status solidi (c) 05/2010; 7(7‐8):1944 - 1948.
• Article: Experimental Demonstration of Novel High-Voltage Epilayer RESURF GaN MOSFET

  Weixiao Huang, T.P. Chow, Y. Niiyama, T. Nomura, S. Yoshida
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  ABSTRACT: We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good tradeoff between breakdown voltage and specific on-resistance for the first time. Device with 4-mum channel length and 16-mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmegamiddotcm² (V_G - V_T = 20 V), best reported to date.
  IEEE Electron Device Letters 11/2009; · 2.85 Impact Factor
• Conference Proceeding: 730V, 34mΩ-cm2 lateral epilayer RESURF GaN MOSFET

  W. Huang, T.P. Chow, Y. Niiyama, T. Nomura, S. Yoshida
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  ABSTRACT: We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good trade-off between breakdown voltage and specific on-resistance for the first time. Device with 4 mum channel length and 16 mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmega-cm² (V_G-V_T=20 V).
  Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
• Conference Proceeding: Enhancement-mode GaN hybrid MOS-HFETs on Si substrates with Over 70 A operation

  H. Kambayashi, Y. Satoh, Y. Niiyama, T. Kokawa, M. Iwami, T. Nomura, S. kato, T.P. Chow
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  ABSTRACT: We report on the demonstration of enhancement-mode n-channel GaN-based hybrid MOS-HFETs realized on AlGaN/GaN heterostructure on silicon substrates with a large drain current operation. The GaN-based hybrid MOS HFETs realized the threshold voltage of 2.8 V, the maximum drain current of over 70 A with the channel width of 340 mm. This is the best value for an enhancement-mode GaN-based FET. The specific on-state resistance was 16.5 mOmegacm². The breakdown voltage was over 500 V. These results suggest that this structure is a good candidate for power switching applications.
  Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
• Conference Proceeding: Enhancement-mode GaN hybrid MOS-HEMTs with breakdown voltage of 1300V

  K. Tang, Z. Li, T.P. Chow, Y. Niiyama, T. Nomura, S. Yoshida
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  ABSTRACT: We have studied and optimized the breakdown voltage of enhancement-mode n-channel GaN hybrid MOS-HEMTs on sapphire substrate. These MOS-gated transistors, with different Mg doped p-type GaN layer underneath the unintentional doped AlGaN/GaN layer, have breakdown voltage as high as 1300 V using a dielectric isolation (DI) RESURF approach.
  Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
• Conference Proceeding: GaAs pseudomorphic HEMTs for low voltage high frequency DC-DC converters

  V. Pala, K. Varadarajan, T.P. Chow
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  ABSTRACT: Efficient power conversion at high switching frequencies requires switching transistors with a low gate charge to limit the switching losses in addition to low specific ON resistance. We report two integrable GaAs switching pHEMTs, 14 V enhancement mode and 7 V depletion mode transistors that show much superior switching figure of merit (R_on times Q_G) than that of state-of-the-art silicon MOSFETs. These transistors can achieve highly efficient DC-DC power conversion at 100 MHz and beyond.
  Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
• Source

  Available from: rpi.edu

  Conference Proceeding: A highly efficient interleaved DC-DC converter using coupled inductors in gaas technology

  Han Peng, T.P. Chow, M. Hella
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  ABSTRACT: This paper presents a high power efficiency DC-DC buck converter in Gallium Arsenide technology targeting integrated power amplifier modules. The buck converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency for a given duty cycle with a minimum penalty on current ripple performance. The DC-DC converter is implemented in 0.5 mum GaAs pHEMT process and occupies 2.7times2.7 mm² without the output network. It converts 4.5 V input to 3.3 V output for 1 A load current under 250 MHz switching frequency with a power efficiency of 86.1%.
  Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
• Article: Over 1500 V/2A operation of GaN RESURF-MOSFETs on sapphire substrate

  Y. Niiyama, H. Kambayashi, S. Ootomo, T. Nomura, S. Kato, T.P. Chow
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  ABSTRACT: A GaN reduced surface field (RESURF) metal oxide semiconductor (MOSFET) on a sapphire substrate is fabricated. The n ^--type RESURF zone was formed by a Si ion implantation technique. The n ⁺- and n ^--type GaN was activated at 1260degC for 30degs in ambient Ar. The sheet carrier densities (activation ratio) of n ⁺- and n ^--GaN were ~3.0~10¹⁵ (~100~) and 1.1~10¹² cm^-2 (1.8%), respectively. As a result, more than 1500%V and 2%A operation of the GaN RESURF MOSFETs is achieved with a channel length of 4%%m, a channel width of 150%mm, and the RESURF length of 20%%m.
  Electronics Letters 04/2009; · 0.96 Impact Factor
• Source

  Available from: R.J. Gutmann

  Article: Fully Monolithic Cellular Buck Converter Design for 3-D Power Delivery

  Jian Sun, D. Giuliano, S. Devarajan, Jian-Qiang Lu, T.P. Chow, R.J. Gutmann
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  ABSTRACT: A fully monolithic interleaved buck dc-dc point-of-load (PoL) converter has been designed and fabricated in a 0.18-mm SiGe BiCMOS process. Target application of the design is 3-D power delivery for future microprocessors, in which the PoL converter will be vertically integrated with the processor using wafer-level 3-D interconnect technologies. Advantages of 3-D power delivery over conventional discrete voltage regulator modules (VRMs) are discussed. The prototype design, using two interleaved buck converter cells each operating at 200 MHz switching frequency and delivering 500 mA output current, is discussed with a focus on the converter power stage and control loop to highlight the tradeoffs unique to such high-frequency, monolithic designs. Measured steady-state and dynamic responses of the fabricated prototype are presented to demonstrate the ability of such monolithic converters to meet the power delivery requirements of future processors.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2009; · 1.22 Impact Factor
• Article: High-Voltage 4H-SiC Bipolar Junction Transistors With Epitaxial Regrowth of the Base Contact

  S. Sharma, C. Li, I.B. Bhat, T.P. Chow
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  ABSTRACT: High-voltage (4-6 kV) 4H-SiC-based bipolar junction transistors were designed, fabricated, and characterized. Various design and process optimization techniques to improve the on state and the forward blocking performance of these devices were studied and incorporated. Using the conventional base contact implantation process, devices with blocking voltages up to 4 kV and specific on-resistance ( R _on, _sp) values higher than the unipolar limit (37 mOmegamiddotcm²), with a current gain of ten in the active region, were experimentally demonstrated. A novel selective growth of p-contact-based process was developed and implemented. This, coupled with improvements in the termination design, resulted in enhancing the blocking voltage capability to 6 kV while simultaneously lowering the R _on, _sp to below the unipolar limit (28 mOmegamiddotcm² and current gain of four in the active region), for the same starting material. Evidence for the presence of conductivity modulation (for the first time) in high-voltage SiC BJTs was also shown experimentally.
  IEEE Transactions on Electron Devices 01/2009; · 2.32 Impact Factor
• Article: The Effect of Gate Oxide Processes on the Performance of 4H-SiC MOSFETs and Gate-Controlled Diodes

  Y. Wang, K. Tang, T. Khan, M. Koushik Balasubramanian, H. Naik, Wei Wang, T.P. Chow
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  ABSTRACT: The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs has been studied. These processes include different gate oxide depositions (high-temperature oxide, low-temperature oxide, and plasma-enhanced chemical vapor deposition oxide) and annealing processes (oxygen, NO, and ). Various MOS device parameters, particularly, threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration, and Hall mobility, are correlated with various process steps.
  IEEE Transactions on Electron Devices 09/2008; · 2.32 Impact Factor
• Conference Proceeding: Modeling of high voltage 4H-SiC JFETs and MOSFETs for power electronics applications

  Yi Wang, C. Cass, Ke Tang, H. Naik, T.P. Chow, D. Boroyevich, F. Wang
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  ABSTRACT: Silicon carbide (SiC), with its high critical electric field property and the capability of operation at high temperature, has attracted much attention and shown to be a promising semiconductor material for high power devices. Some of the most widely used devices in power circuits are the JFETs and the MOSFETs. Based on characterization of high voltage 4H-SiC JFET and MOSFET, this work compares the using of these two kinds of devices in power systems from both electrical and thermal points of view and compact models are developed for circuit simulations.
  Power Electronics Specialists Conference, 2008. PESC 2008. IEEE; 07/2008
• Conference Proceeding: Novel Integrable 80V Silicon Lateral Trench Power MOSFETs for High Frequency DC-DC Converters

  K.R. Varadarajan, A. Sinkar, T.P. Chow
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  ABSTRACT: We propose novel integrable 80V silicon lateral trench power MOSFETs with low Figures of Merit (R_on times Q_g and R_on times Q_gd) proving very attractive for high frequency DC- DC converter applications. The performance of these lateral trench power MOSFETs was simulated using a 2-D device simulator, and an analytical model was developed and implemented in MAST HDL. Circuit simulations indicate a 4X reduction in the switching losses over a comparable commercial device, especially at high switching frequencies ( >500kHz).
  Power Electronics Specialists Conference, 2007. PESC 2007. IEEE; 07/2007
• Conference Proceeding: A Circuit Simulation Model of a Novel Silicon Lateral Trench Power MOSFET for High Frequency Switching Applications

  K.R. Varadarajan, A. Sinkar, T.P. Chow
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  ABSTRACT: In this paper, we present a novel integrable 80 V silicon lateral trench power MOSFET together with its circuit simulation model. The lateral trench power MOSFET exhibits a low figure of merit (R_on times Q_g) proving very attractive for high frequency switching applications. The lateral trench power MOSFET was initially simulated using the 2-D device simulator MEDICI, and an analytical model was developed and implemented in MAST HDL for use in circuit simulators such as SABER. Circuit simulations were performed using the model developed and high frequency switching performance of the proposed device is compared against a commercial device
  Computers in Power Electronics, 2006. COMPEL '06. IEEE Workshops on; 08/2006
• Conference Proceeding: SPICE Model of SiC JFETs for Circuit Simulations

  Y. Wang, Callaway J. Cass, T.P. Chow, F. Wang, D. Boroyevich
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  ABSTRACT: This paper presents SPICE model for one kind of high voltage transistors-1200 V, 5A SiC JFET. Temperature dependent characterization of the device has been done up to 200 degC. Switching behavior has also been studied at 600 V, 5 A level. Based on both static and dynamic characterizations, this paper focuses on SPICE modeling work of such a device for circuit simulations. The model parameters have been extracted from experimental plots. Simulations are then used to verify the developed compact model. Reasonably good agreement has been obtained between the model and experimental results
  Computers in Power Electronics, 2006. COMPEL '06. IEEE Workshops on; 08/2006
• Conference Proceeding: 4 kV, 10 A Bipolar Junction Transistors in 4H-SiC

  S. Krishnaswami, A. Agarwal, J. Richmond, T.P. Chow, B. Geil, K. Jones, C. Scozzie
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  ABSTRACT: 4 kV, 10 A bipolar junction transistors have been demonstrated in 4H-SiC. The device conducts 10 A of collector current with a current gain of 34 at room temperature. The current gain reduces to 21 at 300 degC. Under reverse bias, the device is capable of blocking 4.7 kV with 50 muA leakage current. Room temperature switching measurements show a turn-on time of 168 ns and a turn-off time of 106 ns. These devices show some current gain instability, with the gain decreasing by 50% with time under forward stress. Initial observations reveal the presence of stacking faults in the base-emitter region when the device is forward biased
  Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on; 07/2006
• Article: High Quality MPCVD Epitaxial Diamond Film for Power Device Application

  Jie Yang, Weixiao Huang, T. P. Chow, James E. Butler
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  ABSTRACT: As a wide bandgap (5.47 eV) semiconductor material, single crystal diamond has high electron mobility (reportedly between 2000 and 4400 cm2V-1s-1), high electron saturation velocity (2×107 cms-1), high breakdown voltage (>107 Vcm-1), and high thermal conductivity (>21 Wcm-1K-1). Diamond-based semiconductor devices offer the potential of operation at high voltages, power levels, temperatures and under extreme radiation conditions. In this work, we present our effort to grow high quality homo-epitaxial diamond films on (100)-single crystal diamond substrates by microwave plasma chemical vapor deposition (MPCVD). The growth rate can vary from 0.01 to 100 micrometers per hour, depending on growth conditions, doping, and quality; and using a “lift-off” process, free-standing homo-epi films with remarkably low p-type doping (1×1014–1×1017 cm-3) and exceptionally low compensation ∼ 1×1013 cm-3 have been made. Vertical and lateral structure high voltage diamond Schottky rectifiers have been built for frequency dependent capacitance-voltage (C-V), and current-voltage (I-V) measurements. A breakdown voltage of 8 kV at 100 μm distance and 12.4 kV at 300 μm distance is recorded for lateral structure devices without Ohmic contact (back to back Schottky contacts), while an un-optimized vertical device with an back-side Ohmic contact has demonstrated a forward voltage drop of 7 V at 18 A/cm2 in a device that can only block 600 V. New test results show 3.7 kV blocking voltage vertical devices on 20 μm freestanding MPCVD diamond film. This data shows that the quality of diamond film extremely affect the electrical properties of the built devices.
  MRS Proceedings. 12/2003; 829.
• Article: Electrical characteristics of magnesium-doped gallium nitride junction diodes

  J. B. Fedison, T. P. Chow, H. Lu, I. B. Bhat
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  ABSTRACT: Electrical characteristics of lateral p⁺n diodes made from gallium nitride epitaxial layers on sapphire substrates are reported. The current–voltage characteristics are observed to have several distinct regions in which a tunneling current has been identified at low forward bias in addition to the conventional temperature-dependent diffusion current observed at moderate forward bias. A tunneling behavior indicates the presence of deep-level traps at the junction, which alter the electrical behavior of these junctions compared to the conventional behavior. In addition, space-charge-limited currents are found to influence these junctions at large forward and reverse bias. © 1998 American Institute of Physics.
  Applied Physics Letters 07/1998; · 3.84 Impact Factor