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IEEE Trans. on Circuits and Systems. 01/2012; 59-II:50-54.
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Kyoohyun Lim,
Sunki Min,
Sanghoon Lee,
Jaewoo Park,
Kisub Kang,
Hwahyeong Shin,
Hyunchul Shim,
Sechang Oh,
Sungho Kim,
Jongryul Lee, Changsik Yoo,
Kukjin Chun
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ABSTRACT: This paper describes a fully integrated 130 nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9 GHz, and as well as 5.1-5.9 GHz bands covering whole frequency spectrum of fixed and mobile WiMAX and WLAN. The measured noise figure of the receiver is 3.6-4.2, 4.2-4.7, and 5.4-6.2 dB for each 2/3/5 GHz bands respectively. The measured PLL phase noise from 1 kHz to 10 MHz is 0.5/0.8/0.95 rms degree for 2/3/5 GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to linear RX and TX signal paths and low integrated PLL phase noise characteristics.
IEEE Journal of Solid-State Circuits 08/2011; · 3.23 Impact Factor
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ABSTRACT: An active power-factor correction (PFC) circuit is presented that employs a newly proposed resistor-free zero-current detection (ZCD). While the conventional ZCD requires either a sensing resistor or auxiliary transformer, the proposed ZCD requires only one OFF-chip capacitor. The active PFC circuit with the proposed resistor-free ZCD has been implemented in a 0.35-μm BCDMOS process and the power factor is improved up to 9% from the one employing the conventional ZCD. The proposed resistor-free ZCD scheme can be applied to any type of switch-mode dc-dc power converter.
IEEE Transactions on Power Electronics 03/2011; · 4.65 Impact Factor
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ABSTRACT: A 20 MHz bandwidth continuous-time ΣΔ modulator with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13 μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) DAC for feedback. A new data weighted averaging (DWA) technique is adopted to remove the timing bottleneck at 640 MHz clock frequency. The modulator achieves 63.9 dB peak-SNDR. Dynamic range is 68 dB and decreases by only 2.3 dB when RMS clock jitter is 15 ps. The power consumption is 58 mW from a 1.2 V supply.
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian; 12/2010
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ABSTRACT: A clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is described. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pullin-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13 m CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10<sup>-7</sup> bit error rate (BER) for 2<sup>31</sup>-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.
IEEE Transactions on Consumer Electronics 12/2010; · 0.94 Impact Factor
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ABSTRACT: A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 to 6 GHz in the RF band and from 3.6 to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of the load network. The frequency characteristics of the active-RC channel selection filter with an R-2R ladder is automatically tuned by a one-shot tuning circuit. Implemented in 0.18- μm RF CMOS technology, the whole receive path shows 4.6-5.6-dB noise figure while consuming 65-75 mA from a 1.8-V supply depending on the mode of operation.
IEEE Transactions on Microwave Theory and Techniques 10/2010; · 1.85 Impact Factor
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ABSTRACT: For better electro-magnetic interference (EMI) reduction with minimum hardware increase, a sawtooth dualtone modulation profile has been applied to spread spectrum clock generation (SSCG) phase locked loop (PLL). The SSCG PLL implemented in a 0.18μm CMOS process shows the 23.8dB EMI reduction. This result shows that proposed modulation profile provides 3.5dB better EMI reduction with 39% increased hardware than the conventional triangular modulation profile. For fair comparison of various modulation profiles, a figure of merit (FoM) is introduced and the proposed one shows the best FoM among various modulation profiles.
IEEE Transactions on Consumer Electronics 06/2010; · 0.94 Impact Factor
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ABSTRACT: A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain ( KVCO ) variation was developed. For small KVCO variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 mum CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has -113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.
IEEE Microwave and Wireless Components Letters 09/2009; · 1.72 Impact Factor
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ABSTRACT: A noble automatic frequency calibration (AFC) scheme is proposed for phase-locked loop (PLL) based frequency synthesizer. For fast AFC operation, the frequency control code is updated right after the frequency difference is detected. The uncertainty of the phase relationship between the reference clock and VCO output is eliminated by comparing the divided VCO clock with two-phase reference clocks. The AFC is applied to a CMOS frequency synthesizer. The measured worst case AFC time is less than 1.6 mus. The AFC circuit implemented in a 0.18 mum CMOS process occupies 0.01 mm<sup>2</sup>. The phase noise of the frequency synthesizer output is -113 dBc/Hz at 1 MHz offset from the 4 GHz carrier. The whole frequency synthesizer consumes 23 mW from a 1.8 V supply.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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ABSTRACT: With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mum CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10<sup>-12</sup> bit error rate for 2<sup>31</sup>-1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.
Circuits and Systems II: Express Briefs, IEEE Transactions on 02/2009; · 1.41 Impact Factor
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ABSTRACT: Active-RC biquad is proposed, which allows the DC level of the input of operational amplifier (op-amp) to be different from that of the op-amp output, enabling the low-voltage operation. The proposed biquad realizes a second-order transfer function with only one op-amp, rendering even lower power consumption. By cascading two biquads, a 0.6 V fourth-order filter is realized in a 0.13µm CMOS technology. While dissipating only 0.42 mW, the filter shows 2.11 MHz cut-off frequency and 62 dB spurious-free dynamic range. Copyright © 2008 John Wiley & Sons, Ltd.
International Journal of Circuit Theory and Applications 07/2008; 38(1):99 - 107. · 1.63 Impact Factor
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ABSTRACT: A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 GHz to 6 GHz in the RF band and from 3.6 MHz to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of load network. Implemented in a 0.18 mum 1P5M RF CMOS technology, the whole receive path shows 4.6~5.6 dB noise figure.
VLSI Circuits, 2008 IEEE Symposium on; 07/2008
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ABSTRACT: For low-power and accurate quadrature local oscillator (LO) signal generation, an LC -tank voltage controlled oscillator (VCO) operating at double the required LO-frequency reuses the bias current of divide-by-two frequency divider. The current reusing VCO and divide-by-two frequency divider are targeted to generate the LO signals for a 1.57 GHz global positioning system receiver. Implemented in a 0.18 mum CMOS technology, the current reusing VCO and divide-by-two frequency divider consumes 1.7mA from a 1.8 V supply. The measured phase noise is -120dBc/Hz at 1 MHz offset when the carrier frequency is 1.57GHz.
IEEE Microwave and Wireless Components Letters 07/2008; · 1.72 Impact Factor
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ABSTRACT: A new system interface architecture is proposed for low-cost realization of system-on-glass (SoG) with low-temperature poly-silicon (LTPS) thin-film-transistor (TFT). By re-arranging the order of graphics data transmission, line memory is eliminated, which enables small area and thus lost cost implementation of SoG. Timing controller required for the proposed system interface has been developed for gate and source drivers which are all integrated on the same glass substrate of SoG.
IEEE Transactions on Consumer Electronics 12/2007; · 0.94 Impact Factor
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ABSTRACT: A 1.0V, 10MHz Gm-opamp-C filter is described. For low voltage and high frequency operation, the number of internal nodes
is minimized to avoid the generation of parasitic poles and the number of stacked transistors between VDD and GND is limited
to two. The frequency response of the filter is automatically tuned by a simple self tuning circuit. The measured dynamic
range of the filter is 47dB while dissipating 5mA.
Analog Integrated Circuits and Signal Processing 02/2007; 50(3):285-290. · 0.59 Impact Factor
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ABSTRACT: Fully-integrated CMOS direct-conversion receiver for 5GHz wireless LAN has been developed. To minimize the DC-offset due to LO self-mixing, sub-harmonic mixing is used for down-conversion. For quadrature down-conversion with sub-harmonic mixing, octa-phase LO signals are generated by an integer-N type frequency synthesizer. Implemented in a 0.18mum CMOS technology, the receiver dissipates 97mA from a 1.8V supply voltage and has 6.5dB NF and -4dBm IIP3 from 5.15GHz to 5.35GHz. The phase noise of the closed-loop VCO is -108dBc/Hz at 1MHz offset
Silicon Monolithic Integrated Circuits in RF Systems, 2007 Topical Meeting on; 02/2007
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ABSTRACT: A CMOS multiphase shifting network is described, which is developed for the use in a subharmonic mixing based direct-conversion receiver of 5–6 GHz wireless LAN. Accurate phase shift and amplitude matching are simultaneously achieved with a third-order RC–CR filter followed by the active interpolators whose bias levels are scaled for accurate phase shift. Implemented in a 0.18 μm CMOS process, the phase shifting network provides octa-phase local oscillator (LO) signals spaced by 45°. The measured accuracy of the phase shift and amplitude matching are better than 0.8° and 0.4%, respectively. The phase shifting network excluding LO buffers dissipates 13 mW from a 1.8 V supply voltage. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 118–121, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22033
Microwave and Optical Technology Letters 11/2006; 49(1):118 - 121. · 0.62 Impact Factor
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ABSTRACT: A low phase noise LC-tank quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative g<sub>m </sub> generation and the other one for the coupling input) of each resonator have separate bias current sources which are switched on and off by the coupling input of each resonator. The measured results of 5GHz quadrature VCOs (QVCO) implemented in a 0.13mum CMOS process shows the proposed biasing scheme can improve the phase noise by 17dB from the conventional QVCO with constant tail current sources while the two QVCOs consume the same power (4.4mA from a 1.2V supply). The smaller 1/f noise of the switched current source improves the phase noise by 7dB. The additional 10 dB improvement of the phase noise is obtained by employing the coupling input as the switching signal and separating the tail current sources for the two differential pairs of each resonator
Asian Solid-State Circuits Conference, 2005; 12/2005
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ABSTRACT: A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter - the key building blocks of digital PLL (DPLL), there is no need for the trade-off between jitter, power consumption and silicon area. The DCPLL was implemented in a 0.18mum CMOS process and the active area is 0.35 mm<sup>2</sup>. The DCPLL consumes 59mW during the normal operation and 984muW during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps rms jitter
Asian Solid-State Circuits Conference, 2005; 12/2005
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ABSTRACT: A 1.2V 10MHz low-pass Gm-C filter implemented with low-voltage Gm-cell based on passive resistor and triode-region MOSFET is described. The Gm-cell converts the input voltage to the output current by passive resistor for wider signal swing. For low-voltage operation, triode-region MOS transistors are widely used while the output resistance is improved by regulated gate cascode circuit. The 10MHz low-pass Gm-C filter was implemented in a 0.13μm CMOS technology and the measured input third order intercept point is 3dBV and 9.5dBV, respectively for in-band and out-of-band input.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
