S Uchiyama

Publications (2)0 Total impact

• Conference Proceeding: A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

  M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, Y. Saeki, O. Kato, H. Kikuchi, T. Mitsuhashi
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  ABSTRACT: A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Conference Proceeding: A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology

  Y. Kurita, S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, C. Kakegawa, M. Kawano, Y. Egawa, Y. Saeki, H. Kikuchi, O. Kato, A. Yanagisawa, T. Mitsuhashi, M. Ishino, K. Shibata, S. Uchiyama, J. Yamada, H. Ikeda
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  ABSTRACT: A general-purpose 3D-LSI platform technology for a high-capacity stacked memory integrated on a logic device was developed for high-performance, power-efficient, and scalable computing. SMAFTI technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was introduced for interconnecting the 3D stacked memory and the logic device. A DRAM-compatible manufacturing process was realized through the use of a "via-first" process and highly doped poly-Si through-silicon-vias (TSVs) for vertical traces inside memory dice. A multilayer ultra-thin die stacking process using micro-bump interconnection technology was developed, and Sn-Ag/Cu pillar bumps and Au/Ni backside bumps for memory dice were used for this technology. The vertical integration of stacked DRAM with TSVs and a logic device in a BGA package has been successfully achieved, and actual device operation has been demonstrated for the first time as a 3D-LSI with the DRAM introducing TSVs on the logic device.
  Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th;