R. Gharpurey

University of Texas at Austin, Austin, Texas, United States

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Publications (71)45.19 Total impact

  • T. Forbes, R. Gharpurey
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    ABSTRACT: A frequency-folded ADC-based broadband sampling receiver that merges sampling within the structure of a broadband downconverter is presented. The receiver channelizes a broadband input into sub-bands after digitization, while employing digital-domain harmonic and image rejection. The design offers a frequency-domain approach to simultaneously achieving high sample rate and dynamic range per-unit power consumption. Noise and distortion performance of the architecture is described. An analysis of SNR improvement during signal reconstruction that results from the use of multiple paths at baseband is presented. A 2 GS/s receiver based on this approach is implemented in a 65 nm CMOS process. The receiver spans a bandwidth from 125 MHz to 1000 MHz, and achieves a mean SNDR of 49 dB across the input bandwidth, while providing 38–43.3 dB of gain and a NF of 8.5–13.4 dB. Equalization-based calibration results in harmonic and image rejection greater than 59 dB and 58 dB, respectively, across the input bandwidth, while even better performance may be achieved for tonal interferers. The receiver consumes 104 mW from a dual 1.2/2.5 V supply.
    IEEE Journal of Solid-State Circuits 01/2014; 49(9):1971-1983. · 3.06 Impact Factor
  • T. Forbes, Wei-Gi Ho, Nan Sun, R. Gharpurey
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    ABSTRACT: An analog-to-digital converter (ADC) architecture is described which utilizes mixing instead of high frequency sampling, and folds the input in frequency around harmonics of the mixing local oscillator. The frequency-folded input is separated in the digital domain, which enables significant dynamic range benefits. The frequency of the mixing local oscillator can be significantly smaller than the signal bandwidth, and hence the architecture is suitable for high-speed applications. The architecture is verified through system level simulation and the impact of non-idealities on performance is considered. The design is observed to have a reduced timing skew requirement compared to time-interleaved ADCs.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Wei-Gi Ho, T. Forbes, V. Singh, R. Gharpurey
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    ABSTRACT: A feedback-based active interference suppression technique employing harmonic rejection mixers (HRMs) for enhancing linearity in a broadband channelizer is proposed. In the approach, an interferer is down-converted to baseband, low-pass filtered and then up-converted, where it is subtracted from the input. Using previously reported HRMs capable of LO frequency synthesis in both the down-conversion and up-conversion paths, wideband interference cancellation is achieved without the use of a wide tuning range PLL. Limitation on the maximum achievable interference rejection due to unwanted interaction between inband and out-of-band harmonics is identified. An approach based on a 2-step up-conversion in the feedback path is proposed to remove this limitation. The effectiveness of the proposed technique is verified through simulation.
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on; 01/2013
  • T. Forbes, Wei-Gi Ho, R. Gharpurey
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    ABSTRACT: A harmonic rejection mixer (HRM) with a programmable local oscillator (LO) frequency is presented. The design allows for the generation of multiple effective LO frequencies within a single HRM that are derived from a single primary clock frequency, without any modifications to the analog signal path. A 16-phase HRM with the proposed frequency synthesis technique is implemented in a 130-nm CMOS process. A clocking approach within a two-stage HRM is presented, which reduces HRM sensitivity to both gain and phase mismatch. The HRM synthesizes eight effective LO frequencies and shows an 11.9-dB gain, 11.2-dB DSB NF, and +5.4-dBm in-band IIP3 in the fundamental mode. Greater than 72-dB HR3, 71-dB HR5, and 67-dB HR7 is achieved over ten IC samples in this mode without calibration or harmonic filtering. Harmonic rejection greater than 61 dB for LO factors 2-6 and 54 dB for LO factor 7 is observed, when modifying t 5a8 he effective LO frequency. The HRM achieves S11 better than -10 dB over 50-830 MHz and has a total power consumption of 67 mW from a 1.2-V supply.
    IEEE Journal of Solid-State Circuits 01/2013; 48(10):2363-2374. · 3.06 Impact Factor
  • Jingxue Lu, R. Gharpurey
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    ABSTRACT: A Cartesian transmitter based on pulse width modulation, with the capability to drive a switched power amplifier, such as a Class D stage, is presented. A phase-locked loop based technique is proposed to generate a high frequency pulse width modulated signal with a 1.28 GHz carrier. This signal is subsequently upconverted and applied to the output stage. This technique does not require a ramp generator or a high-precision voltage comparator, that are typically employed in conventional pulse width modulators. A prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a center frequency of 900 MHz. Operation of the architecture with modulation that has a non-constant envelope is verified in simulation.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • T. Forbes, R. Gharpurey
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    ABSTRACT: A method for effective synthesis of multiple downconversion local oscillator (LO) frequencies within a harmonic rejection mixer (HRM) is presented that employs principles similar to direct digital frequency synthesis. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. A passive HRM that implements the proposed LO synthesis method and is robust to both gain and phase mismatch is designed in 130 nm CMOS and covers the 48-860 MHz band with a master clock frequency of 0.77-1.72 GHz. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies.
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on; 01/2012
  • Diptendu Ghosh, Ranjit Gharpurey
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    ABSTRACT: A power-efficient quadrature receiver employing a down-converter that uses a passive current-commutating mixer for frequency translation is presented. The architecture uses bias-current sharing between the RF and baseband stages while making the full supply voltage available to either stage. An input transconductor, realized using a differential common-source stage, converts the RF signal into a current, while baseband amplification is achieved using a transimpedance amplifier. Active noise shaping networks are implemented for reducing low-frequency noise at the output that can arise from the RF and baseband transconductors. Linearity is enhanced by synthesizing a nonlinear gain in the transimpedance amplifier to compensate for baseband compression. The design includes variable gain capability. An on-chip divider is employed to synthesize quadrature LO signals. Noise and linearity performance of the core down-converter is analyzed. The receiver is implemented in a 0.18 $\mu{\hbox{m}}$ CMOS technology. The prototype achieves a maximum conversion gain of 44.5 dB, NF of 4.3 dB, in-channel OIP3 of 20 dBV while consuming 2.2 mA in each of the quadrature paths from a 1.8 V supply. This performance is achieved without the use of integrated inductors, which allows for a small die area of 0.5 mm$ ^{2}$.
    IEEE Journal of Solid-State Circuits 01/2012; 47:381-391. · 3.06 Impact Factor
  • R. Gharpurey
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    ABSTRACT: A key role in determining the overall performance of a communication link is played by the linearity of the analog sections of the transmitter and the receiver. Nonlinearity in the receiver can impact performance in several ways, including degradation in sensitivity, reduction in gain, and the appearance of spurious energy within the frequency band of interest from out-of-band sources. An overview of circuit and architectural techniques for enhancing receiver front-end linearity is presented. Two types of techniques are described, those that rely on device or circuit level linearization, through reduction of nonlinear coefficients, and those that rely on attenuation of undesirable interferers.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2012; 59(8):1667-1679. · 2.24 Impact Factor
  • Sungmin Ock, Jaegan Ko, Ranjit Gharpurey
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    ABSTRACT: A Cartesian Feedback-Feedforward Transmitter for improving the linearity of the transmit path for high-data rate communications is described. A Volterra Series representation is used to analyze the linearity of the architecture. System simulations are used to demonstrate linearity enhancements achieved through a combination of feedback and feedforward. I. INTRODUCTION
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
  • Wei-Gi Ho, Ranjit Gharpurey
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    ABSTRACT: A spectrum sensing technique based on cross- correlation that can be applied to cognitive radios for detection of weak signals is described. It is known that by cross-correlating the outputs of two signal paths, which have independent noise and correlated signals, the sensitivity of the detector can be enhanced. An analog approach to cross-correlation is employed, which avoids the requirement for high dynamic range analog-to- digital converters and digital FFT cores. Each signal path uses an integrated receiver to down-convert the desired portion of the spectrum to baseband for correlation. The use of two-step image- reject down-converters is proposed to alleviate flicker noise and DC offset related degradation that arises in direct-conversion receivers. The impact of finite image rejection in the receivers is addressed and a solution based on offset local oscillator frequencies is proposed. The effectiveness of the approach is validated through simulation.
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
  • Ranjit Gharpurey
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    ABSTRACT: While many narrow-band and single-mode radios have stringent linearity requirements by themselves, these requirements are even more severe in broadband and multimode/multi-band radios. In broadband systems, interferers can appear within the band of interest. In multi-mode systems, the front-end has to satisfy the requirements of multiple standards. In one approach to implementing such radios, individual front-ends can be designed for each standard. This can lead to a large hardware complexity, for instance due to the requirement for custom external band-pass filters and duplexers for each standard. The ideal RFE implementation, on the other hand, should be capable of accommodating all desired standards within a single signal path. While this type of implementation is compact and low-cost, it can impose severe requirements on the front-end, primarily from linearity considerations. In such an implementation, additional interferers could appear within the bandwidth of the frontend. The front-end would need to be designed for the worstcase linearity specification, and the most stringent sensitivity specification, amongst all the standards being considered.
    2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011; 01/2011
  • Jingxue Lu, Ranjit Gharpurey
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    ABSTRACT: A third-order self-oscillating class D audio amplifier that utilizes a hysteretic comparator is presented. The design is an- alyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the require- ment for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion perfor- manceathighoutputpowerlevels.Animplementationispresented in a 0.7 mC MOS process.It achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125mWintoan8 loadat1kHz.TheTHD+Nisunder0.006%up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm . Index Terms—Audio power amplifier, class D, efficiency, hys- teresis,hysteresiscompensation,hystereticcomparator,lowdistor- tion,pulsewidthmodulation,PWM,self-oscillating,SNR,stability, THD.
    IEEE Journal of Solid-State Circuits 01/2011; 46(10):2336-2349. · 3.06 Impact Factor
  • Diptendu Ghosh, Ranjit Gharpurey
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    ABSTRACT: The growth of oscillation in a quadrature oscillator that employs phase shifters in the coupling-path between a pair of LC-loaded negative resistance cores, is analyzed. Such an oscillator is known to have two stable modes of oscillation. Under a noise-initiated startup from an unstable initial condition, quasiharmonic assumption and the Method of First Approximation are used to demonstrate that compression mechanisms lead to preferential enhancement of one mode, while attenuating the other. The magnitude of phase shift in the coupling-path is shown to directly affect the ratio between temporal rates of mode buildup and decay. Index Terms—quadrature oscillator, phase shifter, stable modes, quasiharmonic, first approximation.
    VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011; 01/2011
  • Jingxue Lu, R. Gharpurey
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    ABSTRACT: A low distortion third-order self-oscillating class D audio amplifier is integrated in a 0.7-μm CMOS process. It can deliver 1.4 W into an 8 Ω load with 5 V power supply. The presented amplifier eliminates the requirement for a high quality carrier. It achieves a dynamic range (DR) of 116.5 dB, and a peak THD+N of 0.0012% for a 1 kHz sinusoidal input. The efficiency is 84.5%. The area of the amplifier is 6 mm<sup>2</sup>.
    Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
  • C.K. Eun, R. Gharpurey, Y.B. Gianchandani
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    ABSTRACT: This paper explores the possibility of using microdischarges to generate broadband radio-frequency (RF) signaling from gas-based microdetectors of beta radiation. The concept is evaluated using two types of lithographically manufactured test structures: 1) a silicon/glass stack with etched detection cavities and 2) a planar metal-on-glass structure. The test structures include electrodes that bias a fill-gas region with a high electric field, in which incident beta particles initiate avalanche-driven microdischarge pulses that inherently transmit RF spectra with frequency content extending into the ultrawideband (UWB) range of communication. The discharge gaps range from 165 to 500 μm. The impact of operating pressure, fill gases (which are typically a mixture of Ne and N<sub>2</sub>), and electrode materials (Ni and Cu) on operating voltage and wireless signaling performance is evaluated. Tests are performed in the proximity of weak (0.1-1.0-μCi) beta sources (<sup>90</sup>Sr and <sup>204</sup>TI). Both types of test structures are capable of producing UWB signals spanning > 1 GHz. Measurements in an anechoic chamber using various receiver antennas show that microdischarges can produce field strengths up to 90 dB · μV/m measured at 1.67 m from the test structure.
    Journal of Microelectromechanical Systems 09/2010; · 2.13 Impact Factor
  • D. Ghosh, R. Gharpurey
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    ABSTRACT: A low-power down-converter that uses a passive current-commutating mixer for frequency translation, while sharing the bias current between the RF and baseband stages is presented. An active noise shaping network is implemented to reduce low-frequency noise at the output. Linearity is enhanced through the use of non-linear feedback. The design, implemented in a 0.18 μm CMOS technology, achieves conversion gain of 35 dB, NF of 9.8 dB, in-channel OIP3 of 15.8 dBV while consuming 2.1 mA from a 1.8 V supply.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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    ABSTRACT: This paper discusses the challenges in ultrawideband pulse radio transceiver design and proposes an architecture operating between 3.1 and 10.6 GHz to address them. The 7.5-GHz band is subdivided into multiple channels of 500 MHz each to relax the requirements for pulse generation, transceiver synchronization, and group-delay flatness. The pulse bases for these channels are stored in digital memories and are used for pulse generation on the transmit side and correlation on the receive side. The transceiver can operate in combination with a fast interferer detector that quickly sweeps through the channels to determine which channels are occupied by large interferers and are thus unsuitable for communication. The all-digital pulse bases allow the transceiver to quickly switch between different channels to avoid interferers without needing multiple or, alternatively, broadband fast-settling phase-locked loops. The frequency plan allows the most critical 802.11 interferers to be pushed to higher frequencies during the first block downconversion where they are attenuated by the low-pass filters of the receiver. The wideband intermediate-frequency correlation architecture significantly relaxes the speed requirement of the digital circuit and the local memories. Several signal-processing techniques to eliminate sampling images in the transmitter as well as spurious image responses in the receiver are also presented. The proposed architecture is digitally intensive and, hence, can take advantage of technology scaling.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 03/2010; · 2.24 Impact Factor
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    ABSTRACT: A VCO employing capacitive power combining to reduce phase noise is presented. A current reuse technique is utilized to improve the phase noise per unit power metric over conventional LC oscillators. The VCO achieves a phase noise of -148.7 dBc/Hz at 20 MHz offset and a tuning range of 9.15-10.6 GHz while dissipating 30 mW from a 1.3 V supply. Implemented in a 45 nm CMOS technology, it achieves an FOM of 188 dBc/Hz while occupying an area of 0.67 mm2.
    IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
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    ABSTRACT: This paper presents a new method for testing radio frequency (RF) receivers that utilizes a multitone digital signal generation scheme and relies on the analysis of the receiver baseband output to compute the RF performance parameters. The proposed method takes out the cost of expensive RF instrumentation on the input side of receiver testing and only requires the less expensive baseband digitization at the receiver output. The complexity of the RF signal generation inherent to standard methods is traded off with extensive signal processing on the baseband side, with the tedious analysis necessary for tackling the problem being addressed and presented herein. While the proposed test scheme was implemented and experimentally verified on a load board for testing UHF receivers, generalized use in BIST applications in need of multi-GHz RF stimuli is also discussed in the paper. RF performance parameters like Gain, Noise Figure (NF), and IIP3 were measured using both standard methods and the proposed method and, the results are shown to be accurate.
    28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA; 01/2010
  • F. Zhang, A. Jha, R. Gharpurey, P. Kinget
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    ABSTRACT: A pulse-based CMOS ultra-wideband transmitter and receiver have been realized using a standard digital 90 nm CMOS process. The transceiver uses digital templates stored in high-speed memories for pulse generation on the transmit side and for correlation on the receive side. This allows fast band switching for multi-band operation and interferer avoidance without the requirement for fast-settling phase-locked loops. The receiver contains a 3.1-9.5 GHz broadband front-end and discrete-time intermediate frequency correlators that achieve a pulse rate of 100 Mpulses/s and has a die area of 1 mm<sup>2</sup> while consuming 130 mA from a 1.2 V supply. The transmitter uses interleaved, intermediate frequency digital-to-analog converters followed by partial-order hold reconstruction filters that eliminate sampling images, and a quadrature RF up-converter. 1.25 nJ is spent per transmitted pulse for a pulse-repetition rate of 100 MHz while achieving a broadband image cancellation of 42 dB.
    IEEE Journal of Solid-State Circuits 06/2009; · 3.06 Impact Factor

Publication Stats

876 Citations
45.19 Total Impact Points

Institutions

  • 2005–2012
    • University of Texas at Austin
      • Department of Electrical & Computer Engineering
      Austin, Texas, United States
  • 2005–2010
    • University of Michigan
      • Department of Electrical Engineering and Computer Science (EECS)
      Ann Arbor, MI, United States
  • 2006–2009
    • Columbia University
      • Department of Electrical Engineering
      New York City, NY, United States
  • 1995–2006
    • University of California, Berkeley
      • Department of Electrical Engineering and Computer Sciences
      Berkeley, MO, United States
  • 2004–2005
    • Concordia University–Ann Arbor
      Ann Arbor, Michigan, United States
  • 1995–1999
    • Texas Instruments Inc.
      Dallas, Texas, United States