S. Krishnan

Publications (11)13.18 Total impact

• Article: Scalable PD/SOI CMOS with floating bodies

  J.G. Fossum, M.M. Pelella, S. Krishnan
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  ABSTRACT: An insightful analysis of the floating-body (FB) effect on off-state current (I/sub off/) in PD/SOI MOSFETs is done based on simulations calibrated to a published scaled SOI CMOS technology (Chau et al., 1997). In contrast to the conclusion drawn by Chau, the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with the normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I/sub off/, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.
  IEEE Electron Device Letters 12/1998; · 2.85 Impact Factor
• Conference Proceeding: Control of off-state current in scaled PD/SOI CMOS digital circuits

  M.M. Pelella, J.G. Fossum, S. Krishnan
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  ABSTRACT: A recent study of the scalability of partially depleted (PD) SOI CMOS technology (Chau et al. IEEE IEDM Tech. Dig., p. 591, Dec. 1997) led to the conclusion that it was no better than bulk-Si CMOS for sub-0.25 μm digital applications, irrespective of its inherent advantages, because of the higher threshold voltage (V_T) needed to limit the off-state current (I_off) of the nMOSFET, which tends to be high because of the drain (V_DS)-induced floating-body (FB) effect (i.e. the kink effect) in addition to the barrier lowering (DIBL). In this paper, we give a physically insightful analysis of the FB effect on I_off based on the scaled PD/SOI CMOS technology described by Chau et al. which contradicts the negative assessment of the scalability of SOI digital ICs. Device and circuit simulations of operation at high chip temperatures (55-85°C) that are typical for high-performance circuits show that the FB effect can be naturally ameliorated, and that previously proven techniques for controlling FB effects are also effective in limiting I_off. Furthermore, we show that the temperature coefficient of the body-source voltage (V_BS) is strongly dependent on the recombination current (I_R) of the junctions, and the impact on circuit performance of an increased I_R is shown to be negligible
  SOI Conference, 1998. Proceedings., 1998 IEEE International; 11/1998
• Article: Physical modeling of temperature dependences of SOI CMOS devices and circuits including self-heating

  G.O. Workman, J.G. Fossum, S. Krishnan, M.M. Pelella Jr
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  ABSTRACT: To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature
  IEEE Transactions on Electron Devices 02/1998; · 2.32 Impact Factor
• Article: Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFETs

  M.M. Pelella, J.G. Fossum, Dongwook Suh, S. Krishnan, K.A. Jenkins, M.J. Hargrove
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  ABSTRACT: An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 /spl mu/m SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems.
  IEEE Electron Device Letters 06/1996; · 2.85 Impact Factor
• Article: Subthreshold kinks in fully depleted SOI MOSFET's

  J.G. Fossum, S. Krishnan, O. Faynot, S. Cristoloveanu, C. Raynaud
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  ABSTRACT: Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS.
  IEEE Electron Device Letters 01/1996; · 2.85 Impact Factor
• Conference Proceeding: Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs

  M.M. Pelella, J.G. Fossum, Dongwook Suh, S. Krishnan, K.A. Jenkins
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  ABSTRACT: Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability
  SOI Conference, 1995. Proceedings., 1995 IEEE International; 11/1995
• Conference Proceeding: Floating-body kinks and dynamic effects in fully depleted SOI MOSFETs

  S. Krishnan, J.G. Fossum, P.C. Yeh, O. Faynot, S. Cristoloveanu, J. Gautier
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  ABSTRACT: Fully depleted (FD) SOI CMOS is a contender for low-voltage IC applications. However, as FD/SOI MOSFETs are scaled, floating-body effects, which previously seemed insignificant, become important. In this paper, we report kinks in the measured subthreshold current-voltage characteristics of highly scaled FD/SOI MOSFETs, and we describe and model the underlying physical mechanism, showing how it differs from the familiar kink effect in partially depleted (PD) devices. The insight afforded qualifies the meaning of FD/SOI and implies new design issues for low-voltage SOI CMOS
  SOI Conference, 1995. Proceedings., 1995 IEEE International; 11/1995
• Conference Proceeding: Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology

  S. Krishnan, J.G. Fossum
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  ABSTRACT: Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS
  SOI Conference, 1993. Proceedings., 1993 IEEE International; 11/1993
• Article: Current-drive enhancement limited by carrier velocity saturation in deep-submicrometer fully depleted SOI MOSFETs

  J.G. Fossum, S. Krishnan
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  ABSTRACT: Simulations and measurements of SOI MOSFETs are presented with analytical insight to reveal the severe limitation of current-drive enhancement caused by carrier velocity saturation in the deep-submicrometer fully depleted device. For L =0.1 μm, the enhancement, which tends to result from the suppressed body charge and electric field in the thin-film device, is virtually negated by the velocity saturation driven by the high longitudinal electric field
  IEEE Transactions on Electron Devices 03/1993; · 2.32 Impact Factor
• Conference Proceeding: Performance Limitations of Deep-Submicron Fully Depleted Soi Mosfet's

  J.G. Fossum, S. Krishnan, P.-C. Yeh
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  ABSTRACT: First Page of the Article
  SOI Conference, 1992. IEEE International; 11/1992
• Conference Proceeding: BiMOS modeling for reliable SOI circuit design

  S. Krishnan, J.G. Fossum, M.M. Pelella
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  ABSTRACT: Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits operating at voltages well below the BJT-defined drain-source breakdown. The BJT is also critically important with regard to soft errors in low-voltage SOI memory circuits. In these cases, the BJT current is driven by dynamic charging of the body and concomitant forward biasing of the source (or drain) junction, supported by capacitive, or charge coupling between the BJT and the MOSFET. A reliable circuit model for the floating-body SOI MOSFET must therefore account for the coupled BJT. In this paper we present a new, quasi-2D parasitic BJT model physically coupled to the SOISPICE MOSFET models and defined in terms of their parameters. We further use physical insight derived from this BiMOS modeling to identify a new means of controlling the transient BJT, or leakage current in SOI MOSFETs which could be exploited in design
  SOI Conference, 1996. Proceedings., 1996 IEEE International;