S. Inaba

Toshiba Corporation, Edo, Tōkyō, Japan

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Publications (46)23.27 Total impact

  • Tatsuya Ohguro · Satoshi Inaba · Akio Kaneko · Kimitoshi Okano
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    ABSTRACT: In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H2 annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher fT and fmax, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the fT of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.
    IEICE Transactions on Electronics 01/2015; E98.C(6):455-460. DOI:10.1587/transele.E98.C.455 · 0.39 Impact Factor
  • T. Ohguro · Y. Higashi · K. Okano · S. Inaba · Y. Toyoshima
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    ABSTRACT: In planar MOSFET, the optimization of finger length should be carried out with considering fT, fmax and flicker noise because the noise degradation at STI edge effect appears below 1μm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.
    VLSI Technology (VLSIT), 2012 Symposium on; 01/2012
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    ABSTRACT: Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface and higher thermal stability. The impact of Pt incorporation is widely accepted and recognized in research field; however, the role of Pt in NiSi films has not been fully clarified so far. In this paper, the spatial distributions of Pt and dopants (i.e., arsenic and boron) in silicide films are studied at an atomic level analysis using local electrode atom probe. In particular, Pt and dopant distributions were investigated in detail both at silicide/Si interface and at silicide-grain boundary. Silicide-grain size was also analyzed at various Pt concentrations in silicide films, and the relationship between the Pt concentration and physical properties of Ni<sub>1</sub><sub>-</sub><sub>x</sub>Pt<sub>x</sub>Si films is pointed out. Finally, for further CMOS device scaling, the benefit of higher concentration of Pt incorporation into Ni<sub>1-x</sub>Pt<sub>x</sub>Si films is described.
    IEEE Transactions on Electron Devices 12/2011; 58(11-58):3778 - 3786. DOI:10.1109/TED.2011.2166557 · 2.36 Impact Factor
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    ABSTRACT: We investigated the diffusion of implanted boron and phosphorous in a narrow Si fin during rapid thermal annealing (RTA) at 1000 °C for 10 s. We found that the boron diffusion is described by the conventional diffusion model. We also found that the point defects (interstitial Si and vacancy) play an important role in determining the detailed distribution of boron in a narrow Si fin. On the other hand, the phosphorous diffusion shows anomalous behavior in the peak region of the Si fin, namely large dose loss from the Si region. We found experimentally that about 50% of implanted phosphorous atoms in the Si fin diffused out from the Si region by the annealing (1000 °C, 10 s). The simulation result shows that the experimental result of phosphorous diffusion is reproduced by taking into account the dose loss model through introduction of the interfacial trap layer. Because the phosphorous distribution is largely modified by the dose loss effect, it is considered that the large dose loss of phosphorous gives rise to large impacts on the device characteristics of fin field effect transistors (FinFETs).
    Japanese Journal of Applied Physics 07/2011; 50(7):6506-. DOI:10.1143/JJAP.50.076506 · 1.06 Impact Factor
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    ABSTRACT: Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage ( V <sub>TH</sub>) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low V <sub>TH</sub> variability nMOSFETs with a Si:C-Si epitaxial channel structure.
    IEEE Transactions on Electron Devices 06/2011; 58(5-58):1302 - 1310. DOI:10.1109/TED.2011.2112770 · 2.36 Impact Factor
  • Source
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    ABSTRACT: The impact of plasma doping (PD) on the formation of source/drain extension (SDE) is demonstrated for a p-type bulk fin field effect transistor (FinFET). The impurity distribution in a narrow fin (15 nm) was analyzed with atom probe tomography (APT) and secondary ion mass spectroscopy (SIMS). The lateral distribution of boron in the Si fin by the PD is similar to the case with conventional beam-line ion implantation (BL). However, the vertical distribution of boron by the PD is much steeper than that by the conventional BL. TCAD simulations show that the driving current of the FinFET fabricated by the PD is 34% higher than that of the FinFET fabricated by the BL under the same off-leakage current. Therefore, the PD is a key technology for fabricating the SDE of narrow bulk-FinFETs in the future.
    Japanese Journal of Applied Physics 04/2011; 50. DOI:10.1143/JJAP.50.04DC15 · 1.06 Impact Factor
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    ABSTRACT: Steep channel impurity-profiles formed by Si:C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si:C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: Incorporation of platinum (Pt) into nickel silicide (NiSi) improves the reliability and thermal stability of electrodes in Si MOSFETs. Increasing the Pt content is desirable for further scaled CMOS, but incorporation of more Pt would tremendously increase the material cost. In addition, since Pt is one of the key materials for eco-technology such as catalyst for exhaust absorption and so on, reduction of the use of Pt whose amount is limited is essential for ecology. Recently palladium (Pd), which has similar chemical properties to those of Pt, has been attracting interest as a substitute of Pt. Several works have pointed out that NiPdSi bulk film has superior thermal stability to NiSi. However, its potentiality in fully integrated CMOS devices has not been studied yet. In this work, we investigate the detailed properties of NiPdSi on fully integrated CMOS structures fabricated with the advanced process technology as a candidate of the alternative silicide material for NiPtSi.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2010; DOI:10.1109/VTSA.2010.5488921
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    ABSTRACT: Platinum (Pt)-incorporation into nickel silicide films is the promising approach to reduce the contact resistance (R<sub>C</sub>) at silicide/Si interface. Physical properties of Ni<sub>1-x</sub>Pt<sub>x</sub>Si films were investigated by using local electrode atom probe (LEAP); The distributions of Pt and dopants (such as As and B) were analyzed both at silicide/Si interface and at silicide grain boundary. The silicide grain-size miniaturization was clearly observed by Pt-incorporation. The impacts of silicide grain size on electrical properties and thermal stability were clarified depending on the Pt concentration. Finally, R<sub>C</sub> reduction depending on the incorporated-Pt concentration was experimentally shown in both nMOSFETs and pMOSFETs.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: The trade-off between Tinv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion, components are analyzed in terms of NS, vinj and SCE in Lg= 25 nm devices for the first time. As a result, it is clarified that the aggressive Tinv scaling can achieve the performance improvement even if mu degradation occurs in some degree, because mu impact decreases with Lg and Tinv scaling impact becomes strong. Furthermore, we have introduced the effective Tinv scaling (novel SiON) process and demonstrated its excellent device performance (Ion 1 mA/mum @Ioff=100 nA/mum, Lg 25 nm, Vdd=LOV, Avt=1.8 mV mum, Tinv 1.13 nm, without any performance booster technology).
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    ABSTRACT: In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin width becomes narrower. According to our measurements and simulation analysis, these are because the vertical electrical field from channel to gate electrode has relaxed with narrowing of fin width. The FinFET with narrow fin width is attractive for not only digital but also RF/analog circuits design because of good cut-off characteristics and lower flicker noise.
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    ABSTRACT: The significance of impurity profile design for source/drain extension (SDE) is widely recognized for deeply scaled MOSFET. In this paper, novel SDE formation scheme in planar pMOSFET is discussed using plasma doping (PD) and laser spike annealing (LSA), comparing with conventional Ion Implantation (II) technique. It is found that the combination of PD and high-temperature LSA can realize the abrupt boron profile and an additive efficiency of halo doping in channel region.
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    ABSTRACT: Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-L<sub>G</sub> nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at L<sub>G</sub> of 25 nm are discussed.
    VLSI Technology, 2008 Symposium on; 07/2008
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    ABSTRACT: In this paper, the first systematic study of uniaxial stress effects on mobility (mu)/on-current (I<sub>on</sub>) enhancement and gate current (I<sub>g</sub>) reduction in FinFETs is described. We demonstrate for the first time that I<sub>g</sub> of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher mu/I<sub>on</sub> enhancement ratio by longitudinal strain and comparable/higher short-channel I<sub>dsat</sub>. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.
    VLSI Technology, 2008 Symposium on; 07/2008
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    ABSTRACT: We report TaC<sub>x</sub>/HfSiON gate stack CMOS device with simplified gate 1<sup>st</sup> process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaC<sub>x</sub> composition, fixed charge free TaC<sub>x</sub>/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), L<sub>g</sub> = 35 nm high performance TaC<sub>x</sub>/HfSiON devices is achieved.
    VLSI Technology, 2008 Symposium on; 07/2008
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    ABSTRACT: V<sub>t</sub> variability in FinFET SRAM is evaluated for the first time by direct measurement of the cell transistors down to 25 nm gate length. By taking the V, mismatch between Pull-Down transistors (PD) or between PD & Pass Gate transistor (PG), the dependence of V, variability on the cell transistor layout and channel impurity concentration was clearly observed. Read / Write margins in FinFET SRAM cell are also investigated by measuring both N-curves and their variability. The results suggest that FinFET is still a promising candidate for SRAM applications even in 32 nm node and beyond, if the appropriate cell design is applied.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at V<sub>dd</sub>=1.0 V, I<sub>off</sub> =100 nA/mum at 24 nm gate length, is demonstrated.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
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    ABSTRACT: The transition to sub-90 nm node shifted a paradigm in logic LSI. Traditional device scaling methods failed to boost sufficient performance to uphold Moore's Law. The 90 nm node, therefore, debuted with uniaxial strain engineering to improve device performance. The final scaled gate oxynitride dielectric (<5 atomic layers thick) was also introduced. The 65 nm node continued this scaling path with more enhanced stress inducing films in the front end. Gate dielectric was only slightly scaled at this node. Initial 45 nm node announcements indicate the introduction of immersion lithography, multiple strain inducing films, which use the additivity aspect of various strain inducing films, and PVD hard masks which enhance CD control. The introduction of high-k gate dielectric and metal gate at 45 nm node is hailed as the "'biggest change to computer chips in 40 years". Extrapolation of existing device trends shows significant barriers to the 32 nm technology node. Uniaxial process-induced strain engineering methods, based on new families of ultra-high stress inducing films combined with embedded SiGe or embedded SiC structure at the source/drain, hold promise for achieving 32 nm node device targets. Other process area advances may assist in hitting this mark such as: low resistivity contacts, dual silicides, low-k spacers, single wafer cleans to reduce defect density and eCMP methods with chemistries to reduce variability in lithography and etch. This panel discussion addresses various technologies and lead 32 nm enabling options for further improving CMOS performance. Which sub 32 nm transistor structures are most viable for logic and SRAM applications? What does the future hold for High-k and Metal gate? What are the emerging challenges in device parasitics? What material selection guidelines will keep compatibility between generations? How to control the device characteristic variability? The distinguished panelists will also debate the viability of the above tech- niques to extend Moore's Law toward 32 nm node and beyond.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
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    ABSTRACT: This paper discusses the key FinFET process and integration technologies to achieve high performance LSI. Firstly, side wall pattern transfer technique is introduced to realize an aggressively scaled down FinFET with 10 nm Fin width (W<sub>fin</sub>) and 15 nm gate length (L<sub>g</sub>). Next, dopant segregation (DS) Schottky technique is demonstrated to enhance the FinFET performance. Drive current of 960 muA/mum for DS Schottky nFinFET with L<sub>g</sub> = 15 nm at I<sub>off</sub> = 100 nA/mum and V<sub>d</sub>= 1.0 V is achieved. And then, FinFET SRAM is fabricated and studied in the view of static noise margin (SNM). SNM of 122 mV is obtained in the cell with W<sub>fin</sub> = 15 nm and L<sub>g</sub> = 20 nm at V<sub>d</sub> = 0.6 V. Also, fin height tuning technique is proposed so that SRAM operation can be optimized without area penalty. Finally, integration scheme of planar FET and FinFET is developed and verified to open up the possibility of the future SoC.
    Junction Technology, 2007 International Workshop on; 07/2007
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    ABSTRACT: Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2007