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ABSTRACT: A novel screening platform for the screening and optimization of protein crystallization is reported. Here we present two key experiments to generate protein crystallization phase diagrams. One is to precisely generate spatial gradient droplet arrays; the other is to trap and identify each droplet in place in order to carry out temporal and spatial analysis. The generated concentration and volume gradient ranges from 0% to 100% and from 155 to 310 pico liters, respectively. Furthermore, the active trapping of a droplet array in a microfluidic chip for hours to days to study the dynamic phase changes in protein crystallization is demonstrated. This microfluidic platform can be used for rapidly generating the solubility diagram for protein in various salt solutions.
Engineering in Medicine and Biology Society, 2004. IEMBS '04. 26th Annual International Conference of the IEEE; 10/2004
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S.K.H. Fung,
H.T. Huang,
S.M. Cheng,
K.L. Cheng, S.W. Wang,
Y.P. Wang,
Y.Y. Yao,
C.M. Chu,
S.J. Yang,
W.J. Liang, [......],
H.J. Tao,
C.Y. Fu,
S.M. Jang,
K.F. Yu,
C.H. Wang,
T.C. Ong,
Y.C. See,
C.H. Diaz,
M.S. Liang,
Y.C. Sun
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ABSTRACT: This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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C.H. Diaz,
K.H. Fung,
S.M. Cheng,
K.L. Cheng, S.W. Wang,
H.T. Huang,
Y.K. Leung,
M.H. Tsai,
C.C. Wu,
C.C. Lin,
Mi-Chang Chang,
D. Tang
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ABSTRACT: To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
