R. Kelkar

Publications (4)3.23 Total impact

• Conference Proceeding: A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

  R. Kelkar, D. Flye, A. Malladi, J. Natonio, C. Scoville, K. Short, Pradeep Thiagarajan
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  ABSTRACT: This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described
  SOC Conference, 2005. Proceedings. IEEE International; 10/2005
• Conference Proceeding: A wide-range low-jitter fully integrated programmable frequency synthesizer building block in a 2.5 V/0.25 μm CMOS process

  R. Kelkar, J. Austin, D. Blum, A. Brouillette, T. Frank, C. London, T. Reny, R. Streeter, S. Wyatt
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  ABSTRACT: This paper describes the design of a wide-range programmable frequency synthesizer building block for graphics-application ASICs. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as zero location in order to handle the wide range of divider values. The synthesizer input frequency range is 2.8125 MHz to 200 MHz, while the output frequency is programmable (via dividers) in the range 5.46875 MHz to 350 MHz. A fully integrated, differential structure results in low jitter. The use of BIST (Built In Self Test) for facilitating production testing is also discussed
  ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International; 02/1999
• Article: Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter

  I.I. Novof, J. Austin, R. Kelkar, D. Strayer, S. Wyatt
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  ABSTRACT: A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator
  IEEE Journal of Solid-State Circuits 12/1995; · 3.23 Impact Factor
• Conference Proceeding: Fully-integrated CMOS phase-locked loop with 15 to 240 MHz lockingrange and ±50 ps jitter

  I. Novof, J. Austin, R. Chmela, T. Frank, R. Kelkar, K. Short, D. Strayer, M. Styduhar, S. Wyatt
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  ABSTRACT: Phase-locked loops (PLL) are widely used for clock-phase synchronization, frequency synthesis and clock distribution. It is highly desirable that the standard digital CMOS process be used in the PLL design because process modifications increase product cost. Other desirable features include insensitivity to noise and a fully integrated design. The PLL design reported in this paper has all the above features. A standard digital CMOS process is used to produce a fully differential structure that is immune to substrate and supply noise. The PLL function includes multiplication of frequency and synchronization of input and output clock phases. The architecture is unique because resistors are not needed for PLL loop stabilization
  Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International; 03/1995