S Johnson

Publications (4)0 Total impact

• Source

  Available from: natural-selection.com

  Conference Proceeding: Machine learning approaches for customized docking scores: Modeling of inhibition of Mycobacterium tuberculosis enoyl acyl carrier protein reductase

  G.B. Fogel, J. Tran, S. Johnson, D. Hecht
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  ABSTRACT: Machine learning algorithms were used for feature selection and model generation of customized docking score functions for known inhibitors of Mycobacterium tuberculosis enoyl acyl carrier protein reductase. The features included small molecule descriptors derived from MOE, Accord, and Molegro as well as in silico docking energies/scores from GOLD and Autodock. The resulting models can be used to identify key descriptors for enoyl acyl carrier protein reductase inhibition and are useful for high-throughput screening of novel drug compounds. This paper also evaluates and contrasts several strategies for model generation for quantitative structure-activity relationships.
  Computational Intelligence in Bioinformatics and Computational Biology (CIBCB), 2010 IEEE Symposium on; 06/2010
• Source

  Available from: lw23.com

  Conference Proceeding: 45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process

  S. Yu, J.-P. Lu, F. Mehrad, H. Bu, A. Shanware, M. Ramin, M. Pas, R. Visokay, S. Vitale, S.-H. Yang, [......], H. Hong, J. Tran, R. Chapman, S. Bushman, S. Machala, J. Blatchford, R. Kraft, L. Colombo, S. Johnson, B. McKee
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  ABSTRACT: Bulk CMOS transistors with NiSi fully silicided gate electrodes (FUSI) on plasma nitrided oxide gate dielectric are fabricated by a novel integration method using CoSi₂ as Ni barrier layer on active regions. Performance improvements of 15% (NMOS) and 31% (PMOS) are demonstrated over poly gate electrode transistors at 35 nm gate length. FUSI impact on gate leakage, inversion oxide thickness, V_T variation, and gate oxide reliability are compared to poly gate devices. Dopant modulation of NiSi FUSI gate electrode work-function are studied
  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
• Conference Proceeding: A 1.2V low leakage low cost 90 nm CMOS wireless technology with a 60 nm transistor gate length

  S Yang, G. Pollack, X Wang, S. Potla, G. Baldwin, F Chen, F. Mehrad, T. Tran, K. Sadra, P.R. Chidambaram, S. Chakravarthi, C. Bowen, G. Wells, L. Olsen, J Wu, T. Houston, C. Machala, S Johnson
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  ABSTRACT: In this paper, we have demonstrated a low-leakage low-cost 90 nm technology with a 60 nm gate length for high performance operation by using 193 nm strong-phase-shift lithography, nitrided gate oxide, aggressively scaled MDD junctions and 6-level Cu/low-k interconnects.
  VLSI Technology, Systems, and Applications, 2003 International Symposium on; 11/2003
• Source

  Available from: stanford.edu

  Conference Proceeding: Characterization of Zener-tunneling drain leakage current in high-dose halo implants

  Chang-Hoon Choi, Shyh-Horng Yang, G. Pollack, S. Ekbote, P.R. Chidambaram, S. Johnson, C. Machala, R.W. Dutton
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  ABSTRACT: Degraded junction leakage current in scaled MOSFETs due to enhanced band-to-band tunneling (i.e. local Zener effect) is characterized based on a modified band-to-band tunneling model. To suppress the severe drain leakage current in the presence of high-dose halo implants, the impact of implant conditions on drain leakage current is estimated based on implant induced damage (point defect) profiles.
  Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003