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[show abstract]
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ABSTRACT: A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply
voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled
cascade sense-amplifier circuits have achieved the fast address access
time of 23 ns. A new noise-immune data-latch circuit has attained
power-reduction characteristics at a low operating cycle time without
access delay. A 0.5-μm CMOS, four-level poly, two-level metal
technology with a polysilicon PMOS load memory cell, yielded a small
cell area of 17 μm<sup>2</sup> and the very small standby current. A
quadruple-array, word-decoder architecture allowed a small chip area of
122 mm<sup>2</sup>
IEEE Journal of Solid-State Circuits 11/1990; · 3.23 Impact Factor
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[show abstract]
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ABSTRACT: A 4-Mb (512 K×8) CMOS SRAM that uses a 0.5-μm quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5-μA standby current ( V <sub>cc</sub>=3 V) with a 17-μm<sup>2</sup> memory cell area. A 122-mm<sup>2</sup> (7.2×16.9-mm) chip is achieved by the double-array word-decoder architecture
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International; 03/1990
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K. Sasaki,
S. Hanamura,
K. Ueda,
T. Oono,
O. Minato,
Y. Sakai, S. Meguro,
M. Tsunematsu,
T. Masuhara,
M. Kubotera,
H. Toyoshima
[show abstract]
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ABSTRACT: A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration
has been developed. The RAM was fabricated using 0.8-μm double-poly
and double-aluminum twin-well CMOS technology. A small cell size of 5.2
μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have
been achieved. A fast address access time of 15 ns was achieved using
novel circuit techniques: a PMOS-load decoder and a three-stage dynamic
gain control sense amplifier combined with an equalization technique and
feedback capacitances. A low active current of 50 mA at 20 MHz and low
standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained
IEEE Journal of Solid-State Circuits 11/1988; · 3.23 Impact Factor
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K. Sasaki,
S. Hanamura,
K. Ueda,
T. Oono,
O. Minato,
K. Nishimura,
Y. Sakai, S. Meguro,
M. Tsunematsu,
T. Masuhara,
M. Kubotera,
H. Toyoshima
Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International; 03/1988
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O. Minato,
T. Sasaki,
S. Honjo,
K. Ishibashi,
Y. Sasaki,
N. Moriwaki,
K. Nishimura,
Y. Sakai, S. Meguro,
M. Tsunematsu,
T. Masuhara
[show abstract]
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ABSTRACT: A 128KW×8b RAM with address access time of 42ns and power dissipation of 200mW at 10MHz will be presented. Cell size of 45μm<sup>2</sup>has been achieved by using polysilicon technology and 0.8μm MOS transistors.
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International; 03/1987
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[show abstract]
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ABSTRACT: A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.
IEEE Journal of Solid-State Circuits 11/1985; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm<sup>2</sup>memory cell.
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International; 03/1985
