Publications (6)2.32 Total impact
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Article: Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High-k Control Dielectrics
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ABSTRACT: In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler-Nordheim (FN)/FN mode and a good retention (>; 3 V after ten years) with small activation energy (0.35 eV up to 200 °C), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices.IEEE Transactions on Electron Devices 02/2012; 59(4):933. · 2.32 Impact Factor -
Conference Proceeding: New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling
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ABSTRACT: In this paper, we have studied the charge trapping mechanisms of nitride-based non-volatile memories. The impact of different silicon-nitride (SiN) compositions (standard, std, and Si-rich) on the device characteristics has been investigated through material characterizations, electrical measurements, atomistic and electrical simulations. We found that the different physical nature of the dominant defects in the two SiN compositions is at the origin of the different device electrical behaviors. In particular, we argue that the different electron occupation number of the defect states of the two SiN materials explains the observed faster erasing speed and charge loss rate of Si-rich SiN devices, with respect to std SiN devices, in spite of comparable programming behavior. A simple trap model is proposed to improve state of the art simulators of SiN based memories.Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010 -
Conference Proceeding: Investigation of the role of H-related defects in Al2O3 blocking layer of charge-trap memory retention by atomistic simulations and device physical modelling
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ABSTRACT: In this work, we use atomistic simulation, consolidated by a detailed Al2O3 physico-chemical material analysis, to investigate the origin of traps in Al2O3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al2O3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.IEEE International Electron Devices Meeting, San Francisco, California; 01/2010 -
Conference Proceeding: Performance and Reliability of Si-Nanocrystal Double Layer Memory Devices with High-k Control Dielectrics
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ABSTRACT: In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid Si-nc double layer/SiN layer charge trapping media. These devices show a good memory window and good retention (>3 V after 10 years) with small activation energy (0.35 eV up to 200degC), thus being promising for future high-temperature memory applications.Memory Workshop, 2009. IMW '09. IEEE International; 06/2009 -
Conference Proceeding: New physical model for ultra-scaled 3D nitride-trapping non-volatile memories
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ABSTRACT: In this paper, we present a semi-analytical model tailored for nitride Charge-Trap TriGate (CT-3G) non-volatile memories under uniform stress: Fowler-Nordheim (FN) program (P) and erase (E) performances are reproduced. This model presents innovations in the tunnelling current calculation at corners through the Hankel function formalism. The validation of the model is operated through extensive comparisons with experimental data obtained on ultra-scaled devices with different aspect ratios and gate stacks. Scaling opportunities of such kind of 3D devices are deeply discussed.Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009 -
Article: Investigation of charge-trap memories with AlN based band engineered storage layers
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ABSTRACT: This paper presents the investigation of the electrical properties of charge-trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si3N4 as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si3N4 double layer, which shows reduced program/erase voltages, combined with 106 excellent endurance and good retention (ΔVT > 5 V after 10 years at 125 °C).Solid-State Electronics. 58(1):68-74.
