A. Ghetti

Micron Technology, Inc., Boise, Idaho, United States

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Publications (92)72.36 Total impact

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    ABSTRACT: Discontinuity of electrical and thermal conductivity values at melt has been reported in phase change materials. Signatures of the effect are found in phase change memory cells with Wall architecture. A quantitative model describing the dependence on temperature of electrical and thermal conductivity values of the phase change alloy is introduced, covering the range from solid phase to beyond melt. The model has been implemented in a 3-D electro-thermal TCAD tool and successfully validated against the experimental results.
    IEEE Electron Device Letters 01/2014; 35(7):747-749. · 2.79 Impact Factor
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    ABSTRACT: This paper presents a numerical investigation of the random telegraph noise amplitude in nanoscale MOS devices based on the statistical impedance field method. This method allows a strong reduction of the computational burdens required for the calculation of the amplitude statistics with respect to conventional Monte Carlo models based on the numerical implementation of microscopic differences on the simulated device structure, allowing the exploration of lower probability levels. Despite a rather good estimation of the amplitude statistics, however, the method results in relevant inaccuracies when looking at the single Monte Carlo samples, due to the linear approximations involved.
    Journal of Computational Electronics 12/2013; 12(4):585-591. · 1.01 Impact Factor
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    ABSTRACT: The Phase Change Memory (PCM) technology has followed the scaling roadmap [1] from the 180nm down to the 45nm technology node [2-4], in the last one going in volume production. In a PCM array, thermal crosstalk is referred to as a potential concern due to a temperature raise driven by the programming operation in a cell and its impact on data retention in the neighbor ones. In fact a programming operation in PCM induces a temperature raise in the cell surrounding environment [1]. Such issue has been already addressed in 54nm PCM [5] through an accurate tuning of the programming algorithm. Although effective, such an approach implies several constraints for further optimization of the PCM array performances. In this work we empirically investigate the thermal crosstalk in 45nm PCM arrays, clearly highlighting the key role of the interface thermal resistances engineering. PCM cell design rules for thermal crosstalk immune operation are discussed and implemented on silicon, leading to a fully disturb-immune qualified process.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
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    ABSTRACT: During normal operation of Phase Change Memory (PCM) cells active materials undergo very high electrical and thermal stresses that cause a motion of the different atoms leading to composition variation which has a fundamental impact on performance and reliability. In order to address this issue we introduce here a comprehensive 3D physical model for mass transport in chalcogenide materials. In addition to the driving force for atom diffusion coming from concentration gradient and electric field, the model also accounts for the effect of temperature gradient and phase segregation. This new diffusion model is coupled with a calibrated electro-thermal-phase change model, thus providing a unified framework for the self-consistent simulation of both the electro-thermal and the phase/material change problems. The model is applied to the study of different types of PCM cells showing good agreement with experiments and demonstrating in particular the fundamental role played by the temperature profile.
    2013 IEEE International Electron Devices Meeting (IEDM); 12/2013
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    ABSTRACT: The electrical and thermal parameters of phase change memory (PCM) cells are modified by cycling-induced mechanisms. In this letter, an adaptive cycling procedure is introduced to provide an endurance characterization by keeping the peak temperature at the heater/chalcogenide interface almost constant despite the cell parameters variations. Experimental results on the PCM wall architecture are collected and explained by considering the reduction of the heater electrical/thermal resistances and the impact of crystallization kinetics variation during cycling.
    IEEE Electron Device Letters 07/2013; 34(7):882-884. · 2.79 Impact Factor
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    ABSTRACT: This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.
    IEEE Electron Device Letters 05/2013; 34(5):683-685. · 2.79 Impact Factor
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    ABSTRACT: This work investigates the performance of the statistical impedance field method in the analysis of the amplitude of random telegraph noise fluctuations in nanoscale MOS devices. Considering different channel doping profiles, we show that this method offers a practical compromise between accuracy and computational loads, allowing a good assessment of the RTN amplitude statistics while resulting in non-negligible errors on the single microscopic samples where atomistic doping strongly contributes to non-uniformities of channel inversion and to percolative source-to-drain conduction.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013
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    ABSTRACT: This paper presents a detailed experimental and numerical investigation of the variability of the band-to-band leakage current of p-n junctions in nanoscale MOS devices. The experimental results reveal that this leakage follows a log-normal statistical distribution, whose spread, barely affected by temperature, increases as junction scaling proceeds. These features are correctly reproduced by 3-D device simulations, whose results allow to identify in atomistic doping the main origin of the leakage statistical dispersion.
    IEEE Transactions on Electron Devices 01/2013; 60(10):3291-3297. · 2.06 Impact Factor
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    ABSTRACT: This paper is aimed at exploring efficient approaches for the simulation of Random Telegraph Noise (RTN) in variability analysis of advanced floating gate non-volatile memories. RTN is traced back to randomly occupied localized traps located close to the Si/SiO2 interface. While the effect of traps has been investigated previously by means of time-consuming Monte Carlo simulations [1], in this work we try to exploit an efficient Green Function based analysis, akin to the one implemented in Synopsys SDevice for Random Doping Fluctuations (RDF) [2].
    Noise and Fluctuations (ICNF), 2013 22nd International Conference on; 01/2013
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    ABSTRACT: This paper presents a comprehensive numerical study of the impact of cell shape on random telegraph noise (RTN) in nanoscale Flash memory devices. The statistical dispersion of the RTN fluctuation amplitude is computed using both classical and quantum-corrected 3-D TCAD simulations of devices featuring three different active-area shapes (planar, rounded edges, and full rounded), with self-aligned or surrounding floating gate. For both the floating-gate geometries, results show that RTN immunity is enhanced by increasing the rounding of the active-area edges in the width direction, due to a more uniform source-to-drain conduction during read. For this analysis, the importance of quantum-mechanical corrections for the correct evaluation of the RTN distribution of sharp-edge devices is highlighted. Finally, the reduction of RTN by cell shape engineering is shown to be anticorrelated with the reduction of cell threshold-voltage variability.
    IEEE Transactions on Electron Devices 10/2012; 59(10):2774-2779. · 2.06 Impact Factor
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    ABSTRACT: This paper presents a thorough numerical investigation of the effect of nonuniform doping on random telegraph noise (RTN) in nanoscale Flash memory devices. For a fixed average threshold voltage, the statistical distribution of the RTN fluctuation amplitude is studied with nonconstant doping concentrations in the length, width, or depth direction in the channel, showing that doping increase at the active area corners and retrograde and $\delta$-shape dopings appear as the most promising profiles for RTN suppression. In particular, the improvements offered by retrograde and $ \delta$-shape dopings increase the more the high doping regions are pushed far from the channel surface due to a more uniform source-to-drain conduction during read. Finally, the suppression of RTN by engineered doping profiles is correlated with the reduction in cell threshold voltage variability.
    IEEE Transactions on Electron Devices 02/2012; 59(2):309-315. · 2.06 Impact Factor
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    ABSTRACT: We show here for the first time that the band-to-band (B2B) leakage current of nanoscale p-n junctions has a significant statistical dispersion caused by the atomistic nature of both the n-type and the p-type doping. As a result, the B2B current displays a log-normal distribution, with a spread increasing with the scaling of the junction width. This spread may largely increase the average device leakage and, in turn, increase power dissipation in future technologies.
    Electron Devices Meeting (IEDM), 2012 IEEE International; 01/2012
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    ABSTRACT: For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.
    IEEE Transactions on Electron Devices 01/2012; · 2.06 Impact Factor
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    ABSTRACT: In this paper we present a detailed simulation analysis of the impact of the substrate doping profile on Random Telegraph Noise (RTN) instabilities in deca-nanometer Floating Gate Flash memories. Following a Monte Carlo procedure, the statistical distribution of the RTN fluctuation amplitude has been computed running a large number of 3D device simulations, with random placement of discrete dopant atoms in the substrate and a discrete single trap at the Oxide/Substrate interface. To explore the effect of the doping profile on RTN instabilities, both retrograde and δ-shape dopings have been investigated, considering their optimal parameters for RTN suppression. This analysis allows to clarify several key issues relating the substrate doping profile and the RTN distribution amplitude. Results are of utmost importance for the assessment of design guidelines for technology optimization against RTN instabilities.
    01/2011;
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    ABSTRACT: Referring to a template deca-nanometer Flash cell, we show for the first time that 3D electrostatics and atomistic doping play an essential role in the time constants of random telegraph noise in nanoscale MOS devices, resulting in a several orders-of-magnitude spread in their values and in their negligible correlation with the noise fluctuation amplitude. These results reveal that any 1D method for trap spectroscopy is intrinsically flawed when applied to nanoscale devices, and also question the possibility of correctly extracting the physical trap parameters.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2011;
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    ABSTRACT: This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.
    IEEE Transactions on Electron Devices 10/2010; · 2.06 Impact Factor
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    ABSTRACT: In this paper the modelling approaches for determination of the drain current in nanoscale MOSFETs pursued by various partners in the frame of the European Projects Pullnano and Nanosil are mutually compared in terms of drain current and internal quantities (average velocity and inversion charge). The comparison has been carried out by simulating template devices representative of 22 nm Double-Gate and 32 nm Single-Gate FD-SOI. A large variety of simulation models has been considered, ranging from drift-diffusion to direct solutions of the Boltzmann-Transport-Equation. The predictions of the different approaches for the 32 nm device are quite similar. Simulations of the 22 nm device instead, are much less consistent. Comparison with experimental data for a 32 nm device shows that the modeling approach used to explain the mobility reduction induced by the high-k dielectric is critical.
    Microelectronics Proceedings (MIEL), 2010 27th International Conference on; 06/2010
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    ABSTRACT: Some of the largest semiconductor companies involved in the non volatile memory business have demonstrated that Phase-Change Memory (PCM) technology has today reached the product maturity at 90 and 65 nm nodes and 45 nm platform is under development. In this approaches the architectural choice for large density arrays decoding relies on silicon diodes or BJT-selected PCMs (BJT-PCM), thus defining it as the mainstream PCM non-volatile memory technology. However to continue the PCM technology scaling roadmap the current density required to program the storage element will increase linearly with the lithography reduction, becoming of the order of tens of MA/cm<sup>2</sup> in the BJT selector and of hundreds of MA/cm<sup>2</sup> in the storage element at ultra-scaled lithographic nodes. In the ITRS 2008 the maximum current density to program a PCM cell has been recognized as the main physical mechanism that can impact the reliability of scaled PCM devices and it can be a serious show-stopper for this technology beyond the 32 nm technology node. Aim of this paper is to investigate the impact of the increasing current density on the functionality and reliability of scaled BJT-PCM architecture down to the 16 nm node.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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    ABSTRACT: This paper presents a new cell crosstalk effect in deca-nanometer nand Flash memories, making the data retention and erase transients of fresh cells dependent on the threshold-voltage level at which adjacent cells in the array are placed. In particular, a programmed cell is shown to display a larger threshold-voltage loss when its adjacent cells are in the erased than in the programmed state, with cells on the same bit line and word line having a similar impact on the acceleration of the threshold-voltage loss. The effect is explained by means of 3-D TCAD simulations, showing that a low threshold voltage for the adjacent cells increases the discharging tunneling current of the monitored cell for a fixed negative potential of its floating gate. This is due to a change of the electric field profile at the corners of the monitored cell active area when the potential of the floating gate of its neighboring cells is modified.
    IEEE Transactions on Electron Devices 02/2010; · 2.06 Impact Factor
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    ABSTRACT: We present a comprehensive investigation of the programming dynamics of nanoscale charge-trap memories, based on 3D Monte Carlo simulations accounting for: 1) true 3D electro-statics during programming and read; 2) atomistic substrate doping; 3) discrete traps, fluctuating in number and position, with localized electron storage; 4) discrete electron injection into traps. The model allows to clarify several key issues affecting the program operation of charge-trap memories, most notably the reduced slope of the ISPP transients exhibited by scaled cells, the programming variability, and the width of the final programmed threshold-voltage distribution. Results are of utmost importance for the assessment of the true programming performance of nanoscale charge-trap memory technologies.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010;

Publication Stats

834 Citations
72.36 Total Impact Points

Institutions

  • 2013
    • Micron Technology, Inc.
      Boise, Idaho, United States
  • 1999–2009
    • University of Udine
      • Department of Electrical, Management and Mechanical Engineering
      Udine, Friuli Venezia Giulia, Italy
  • 2004–2008
    • Politecnico di Milano
      • Department of Electronics, Information, and Bioengineering
      Milano, Lombardy, Italy
  • 2000
    • STMicroelectronics
      Genève, Geneva, Switzerland
  • 1999–2000
    • Alcatel Lucent
      Lutetia Parisorum, Île-de-France, France
  • 1995–1999
    • University of Bologna
      • "Guglielmo Marconi" Department of Electrical, Electronic and Information Engineering DEI
      Bologna, Emilia-Romagna, Italy
  • 1998
    • AT&T Labs
      Austin, Texas, United States
  • 1997
    • Università degli studi di Parma
      Parma, Emilia-Romagna, Italy