[Show abstract][Hide abstract] ABSTRACT: This paper presents the opportunities and challenges for scaling A/D converters into ultra-deep-submicron CMOS technologies. With faster transistors and better matching, the trend is to migrate into higher sample rates with lower resolutions. Limited dynamic range at low supply voltages remains the utmost challenge for high-resolution Nyquist converters, and oversampling will become the dominant technique in this arena in the future. Linearity correction with digital calibration is also becoming prevalent as the efficiency of calibration circuitry improves
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
[Show abstract][Hide abstract] ABSTRACT: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-μm 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm<sup>2</sup> and dissipates 98 mW.
IEEE Journal of Solid-State Circuits 01/2005; · 3.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm<sup>2</sup> in 0.18 μm CMOS and dissipates 112 mW.
[Show abstract][Hide abstract] ABSTRACT: We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.
Circuits and Systems I: Regular Papers, IEEE Transactions on 02/2004; · 2.24 Impact Factor