Yoji Kajitani

Kitakyushu University, Kitakyūshū, Fukuoka, Japan

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Publications (100)13.51 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Lately, time-multiplexed I/Os for multi-device implementations (e.g., multi-FPGA systems), have come into practical use. They realize multiple I/O signal transmissions between two devices in one system clock cycle using one I/O wire between the devices and multiple 1/0 clock cycles. Though they ease the limitation of the number of I/O-pins of each device, the system clock period becomes much longer approximately in proprotion to the maximum number of multiplexed I/Os on a signal path. There is no conventional partitioning algorithm considering the effect of time-multiplexed I/Os directly. We introduce a new cost function for evaluating the suitability of a bipartition for multi-device implementations with time-multiplexed I/Os. We propose a performance-driven bipartitioning method VIOP which minimizes the value of the cost function. Our method VIOP combines three algorithms, such that i) min-cut partitioning, ii) coarse performance-driven partitioning, iii) fine performance-driven partitioning. For min-cut partitioning and coarse performance-driven partitioning, we employ a well-known conventional bipartitioning algorithms CLIP-FM and DUBA, respectively. For fine performance-driven partitioning for the final improvement of a partition, we propose a partitioning algorithm CAVP. By our method VIOP, the average cost was improved by 10.4% compared with the well-known algorithms.
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 05/2007; 90-A(5):924-931. DOI:10.1093/ietfec/e90-a.5.924 · 0.23 Impact Factor
  • Shuichi Ueno, Yoji Kajitani, Hajime Wada
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    ABSTRACT: This paper solves the minimum augmentation problem for a given tree and positive integer k, that is, to make a tree k-edge-connected by adding the minimum number of edges. It is shown that the minimum number of edges is the least integer not less than a half of the deficiency of the tree which is defined as the sum of k-(degree) over all the vertices whose degrees are less than k. The proof is constructive and gives a polynomial-time algorithm for constructing such an augmentation.
    Networks 10/2006; 18(1):19 - 25. DOI:10.1002/net.3230180104 · 0.74 Impact Factor
  • Yoji Kajitani
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    ABSTRACT: After BSG and sequence-pair (SP) of the placement codes, a decade has passed with various proposals of new codes and ideas for applications, especially in VLSI physical design. Different in appearance, they are actually proposing generators of ABLR-relations, i.e. above, below, left-of, or right-of relations between two rectangles on a plane to be non-overlapping, together with methodologies how dimensions and peripheral constraints are integrated. This paper proposes another yet simplest generator numDAG which is simply a directed acyclic graph with vertices labelled with distinct numbers. Assuming each vertex representing a rectangle on a plane, an edge (i, j) is featured to imply the property "i is left-of j" or "i is above j" according to the edge being incremental or decremental, respectively, with respect to the numbers of end vertices. To demonstrate that the numDAG is the ABLR-relation generating system hierarchically above existing systems, we relate it with single-sequence, H-and V-constraint graph pair, SP, BSG, and O-tree. It is a future problem to find any practical merit by this idea but the contribution is believed in providing a base to the unified theory of constraint-driven placement. Several new ideas and problems are included
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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    ABSTRACT: Analog layout automation is one of the most challenging subjects that has to cope with trade-offs among analog specific requirements such as noise, linearity, gain, supply-voltage, speed, power consumption, etc. This paper proposes a novel porting methodology that guides the reuse of analog IPs, followed by an automation system. The methodology introduces a concept of conservative properties that are necessary and sufficient for the configuration of the high quality layout. The properties are extracted from schematics and the past layouts, and then are represented in terms of module configurations and topological constraints imposed on devices. In experiments, our porting system is applied to several industrial analog circuits. In the design of an A/D converter, we ported the layout on 0.20mum/3.3V technology to that on 0.18mum/1.8V technology. The result not only met the required performance, but also achieved the comparable quality with the manual layout. The design time was reduced drastically
    Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on; 04/2006
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    ABSTRACT: The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 02/2006; E89-A(2):448-455. DOI:10.1093/ietfec/e89-a.2.448 · 0.23 Impact Factor
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    ABSTRACT: The recent hierarchical design framework[8] for 3D floorplan-ning suggests a better performance than previous flat design framework. Under this framework, the layer assignment of the blocks is accomplished by some partitioning algorithms which are assumed to be critical[8]. In this paper, we provide an empirical study on the impact of such partitioning algorithms on the total wire length. By generating various partitions and running our floorplanner based on these partitions, we obtain the statistic of the resultant wire length. We observe that when the design instance has a large number of blocks which are uniformly sized, different partitions with the same cut size lead to roughly the same wire length. By another experiment, we find out that the cut size of the partition has the major influence on the wire length. Therefore, we argue that cut size is a metric good enough for the wire length optimization of 3D floorplanning and suggest that future research focus on other problems such as thermal effect, signal delay, etc.
    Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006; 01/2006
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    ABSTRACT: For multi-FPGA systems, the limitation of the number of FPGA I/O-pins is one of the most critical issues. Using time-multiplexed I/Os eases the limitation. While, a signal path through n time-multiplexed I/Os makes the system clock period n + 1 times longer at most. To capture this feature, we introduce a new cost total cut-hopcount. Under the total cut-hopcount, we propose a performance-driven bipartitioning method VIOP. VIOP combines three algorithms, such that i) min-cut partitioning, ii) coarse performance-driven partitioning, and iii) fine performance-driven partitioning. For min-cut and coarse performance-driven partitioning, we employ well-known bipartitioning algorithms CLIP-FM and DUBA, respectively. For fine performance-driven partitioning, we propose a partitioning algorithm CAVP. By VIOP, the average cost was improved by 11.5% compared with the state-of-the-art algorithms
  • Xuliang Zhang, Xiaoke Zhu, Y. Kajitani
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    ABSTRACT: Due to layout or specific physical requirements in deep sub-micron technology, integrated circuit blocks can be in an arbitrary rectilinear shape. Much research has been done to deal with convex and concave rectilinear blocks. However, it is still not enough to solve the problem perfectly. We apply the newly reported placement representation tool, SS (single-sequence), to solve this problem.
    Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on; 06/2005
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    ABSTRACT: FPGA placement is a two dimensional placement problem. But recent generations of FPGA allow run-time dynamic reconfiguration. We extend another dimension denoting execution time, so the optimization of the dynamic hardware reconfiguration problem becomes a three dimensional rectangle placement problem with spatial and temporal constraints. In this paper, we propose a new deterministic algorithm LFF (less flexibility first principle), which is derived from human accumulated experience and first presented for a two dimensional packing problem, to solve this problem. Good experimental results show that LFF is very effective and promising.
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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    ABSTRACT: The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, any practically useful path finding and shape-based sizing technique are executed on the same architecture. Our system ex-perimentally demonstrates the performance comparable to a commercial tool.
    Proceedings of the 15th ACM Great Lakes symposium on VLSI; 04/2005
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    ABSTRACT: A new algorithm addressed to fixed-outline floorplanning is proposed. The proposed algorithm differs from general simulated annealing based algorithms in that it starts with a sub-instance (i.e. instance with fewer modules) of the given floorplanning instance and progressively augments the sub-instance until a feasible solution of the given instance is found. Experimental results show that the proposed algorithm is quite promising in fixed-outline floorplanning, even when tight outline and boundary and pre-placed constraints are imposed.
    International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan; 01/2005
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    ABSTRACT: In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n⩾3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability.
    Integration the VLSI Journal 01/2005; 38(3-38):439-449. DOI:10.1016/j.vlsi.2004.07.008 · 0.53 Impact Factor
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    ABSTRACT: A new compact code called EQ-sequence for representing a floorplan is presented. A floorplan decides the placement of modules in VLSI design. The EQ-sequence is developed from Q-sequence and it can preserve the adjacent relationships of rooms on a floorplan, but the Q-sequence cannot. The algorithms for encoding, moving and decoding of EQ-sequences are introduced, respectively. By the EQ-sequence, we can check whether two modules abut or not on a floorplan. It has been proved that any floorplan of n rooms is uniquely encoded by an EQ-sequence and any EQ-sequence is uniquely decoded to a floorplan, both are in O(n) time.
    Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on; 08/2004
  • Xuliang Zhang, Y. Kajitani
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    ABSTRACT: The single-sequence (SS) debuted very recently as the literally simplest code to represent the consistent ABLR-relations (above, below, left-of, right-of) between every pair of objects. It is evolutional in several senses in that it does not convey the labels of objects and that objects could be either physical modules or topological rooms of a T-junction floorplan. Rather it is considered an extremal abstraction of those BSG, SP, O-Tree, etc. algorithms (for packing) and Q-seq, CBL, HPG, etc. (for floorplanning). The paper reports a discovery of a particular relation between SS and the normalized configuration of the floorplan called the unit-diagonal diagram.
    Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on; 07/2004
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    ABSTRACT: The slicing floorplan has been intensively researched for its naive property to cut-based placement, soft-module packing, designers' intention even after packing and general floorplan representations were proposed. HPG, one easy-to-understand general floorplan representation, was proved to get the optimal solution in a shorter time than other representations. In this paper, we present an algorithm to show another outstanding feature of HPG. By using this algorithm, we can search and find the optimal slicing floorplan easily, which can provide more flexibility for placement and routing tools. Experiments show the effectiveness and promising perspective of our algorithm.
    Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on; 07/2004
  • Xiaoke Zhu, Changwen Zhuang, Y. Kajitani
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    ABSTRACT: The single-sequence (SS) is simply a sequence of integers 1, 2, 3, ..., n. But it leads a unique set of ABLR-relations (above, below, left-of, right-of) that hold among n objects on a plane. The direct relation set (DRS) is used to represent the direct ABLR-relations among rooms. It can be reused for any packing under the same floorplan. In this paper we analyze the relation between DRS and SS, and propose a general packing algorithm based on SS. It can update each room's coordinates on the fly. As a feature of SS, this algorithm covers all possible placements, if our objective is in bounding-box area minimization. Experimental results showed that the proposed algorithm is pretty fast and efficient compared with the performance attained by conventional algorithms.
    Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on; 07/2004
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    ABSTRACT: Although the bounded sliceline grid (BSG) is an effective data structure for treating rectangular placement, it needs to deal with more complicated rectilinear figures such as L- or T-shaped figures in its applications to VLSI layouts. A number of studies have been conducted regarding this problem, but the methods considered in these studies not only have not considered representation of the optimal placement of complicated rectilinear figures but also have not generated permissible neighboring solutions, and searching optimal solutions by search schemes based on these methods is difficult. In order to resolve this problem, this paper proposes multilayered parametric BSG and a placement algorithm using the multilayered parametric BSG. Multilayering allows descriptions representing conditions for nonoverlapping of rectilinear figures simultaneously with constraints of each layer. Parameterization allows multiple solutions represented by the BSG. The proposed method represents complicated rectilinear figures as combinations of a number of element rectangles. When a figure (core cell) with the element rectangles having common parts is the input, it gives the conditions of the multilayered parametric BSG guaranteeing the possibility of generating an optimal solution in terms of the surface area. The practicability of the idea of the proposed method has been verified by testing with several tens of figure inputs by implementing an optimal solution search algorithm based on simulated annealing based on the proposed data structure. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(7): 66–78, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10079
    Electronics and Communications in Japan (Part III Fundamental Electronic Science) 07/2004; 87(7):66 - 78. DOI:10.1002/ecjc.10079 · 0.14 Impact Factor
  • Xuliang Zhang, Y. Kajitani
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    ABSTRACT: In a placement, two rectangles on a plane are non-overlapping if and only if the relationship between them is one of ABLR (above, below, left-of, right-of)-relations. From the standpoint that a system of ABLR-relations is specified by the designer to confine the placement, the first concern is its consistency, i.e. if there is a corresponding placement. The second is an efficient way to construct a corresponding placement. The third is a handy coding of the ABLR-system all the way. In this paper, the first concern is solved by an existence condition of the primal-and dual-orders of rectangles. The second is answered by a linear time construction algorithm of a T-junction floorplan. This is new in its speed and generality with respect to the number of rooms. The third is by a new coding single-sequence SS. Its unique suitability to handle the T-junction floorplan is remarkable. Using the merit that SS can control the distribution of empty rooms, a novel application is suggested to space-planning, a recent trend in VLSI physical design to budget the space for congestion relief and interference separation (though the detail is not contained here for the space).
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
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    N. Fu, S. Nakatake, Y. Takashima, Y. Kajitani
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    ABSTRACT: We aim at developing floorplan method, a key in topdown design of system LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length.
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific; 02/2004

Publication Stats

2k Citations
13.51 Total Impact Points

Institutions

  • 2001–2007
    • Kitakyushu University
      • Department of Information and Media Engineering
      Kitakyūshū, Fukuoka, Japan
  • 1988–2006
    • Tokyo Institute of Technology
      • Electrical and Electronic Engineering Department
      Edo, Tōkyō, Japan
  • 2002
    • Fukuoka University
      Hukuoka, Fukuoka, Japan
  • 1998
    • University of California, Berkeley
      • Department of Electrical Engineering and Computer Sciences
      Berkeley, California, United States
  • 1995–1997
    • Japan Advanced Institute of Science and Technology
      • School of Information Science
      KMQ, Ishikawa, Japan