-
[show abstract]
[hide abstract]
ABSTRACT: A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 μm<sup>2</sup> has been developed using 0.5-μm technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O<sub>2</sub> annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on; 07/1998
-
K. Torii,
H. Kawakami,
H. Miki,
K. Kushida,
T. Itoga,
Y. Goto,
T. Kumihashi, N. Yokoyama,
M. Moniwa,
K. Shoji,
T. Kaga,
Y. Fujisaki
Integrated Ferroelectrics 04/1997; 16(1-4):21-28. · 0.30 Impact Factor
-
K. Shoji,
M. Moniwa,
H. Yamashita,
T. Kisu,
T. Kaga,
K. Torri,
T. Kumihashi,
T. Morimoto,
H. Kawakami,
Y. Gotoh,
T. Itoga,
T. Tanaka, N. Yokoyama,
T. Kure,
M. Ohkura,
Y. Fujisaki,
K. Sakata,
K. Kimura
[show abstract]
[hide abstract]
ABSTRACT: A ferroelectric memory cell with an area of only 7.03 μm<sup>2
</sup> designed with a 0.5-μm rule has been fabricated. It performs
Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and
automatic nonvolatile writing when Vcc is shut down. A non-separated
plate electrode and a capacitor patterned by one-mask dry etching reduce
cell area. Planarization of the poly-Si plugs and the use of H-less
metallization/passivation processes retain the PZT capacitor
characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read
under ±2.5-V operation in 4-K bit memory cell arrays
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on; 07/1996
-
T. Sakata,
M. Horiguchi,
T. Sekiguchi,
S. Ueda,
H. Tanaka,
E. Yamasaki,
Y. Nakagome,
M. Aoki,
T. Kaga,
M. Ohkura, [......],
F. Murai,
T. Tanaka,
S. Iijima, N. Yokoyama,
Y. Gotoh,
I. Shoji,
T. Kisu,
H. Yamashita,
T. Nishida,
E. Takeda
[show abstract]
[hide abstract]
ABSTRACT: A distributed-column-control architecture is proposed to reduce
the burst-mode cycle time of large-capacity DRAMs. It features
independent operation of the I/O block and subarrays, eliminating the
wiring delay in the internal buses from the longest pipeline stage. The
timing difference between the I/O block and the subarrays is compensated
for by event-driven circuits. This architecture also eliminates the
timing margin between the activation of column selection lines, reducing
the cycle time by 25%. To evaluate this architecture, an experimental
synchronously operating 1-Gb DRAM was designed and fabricated using a
0.16-μm CMOS process. It operates with a 22O-MHz clock and a 1.5-V
power supply
IEEE Journal of Solid-State Circuits 12/1995; · 3.23 Impact Factor
-
M. Horiguchi,
T. Sakata,
T. Sekiguchi,
S. Ueda,
H. Tanaka,
E. Yamasaki,
Y. Nakagome,
M. Aoki,
I. Kaga,
M. Ohkura, [......],
F. Murai,
T. Tanaka,
S. Iijima, N. Yokoyama,
Y. Gotoh,
K. Shoji,
T. Kisu,
H. Yamashita,
T. Nishida,
E. Takeda
[show abstract]
[hide abstract]
ABSTRACT: With the arrival of the multimedia era, high-data-rate memory LSIs
are becoming increasingly important to keep up with high-speed CPUs,
graphics processors, and other consumers of stored data. Video editing
and replaying of high-definition television in particular require a high
bandwidth. This paper presents two circuit technologies for a
synchronously operating high-data-rate 1 Gb DRAM: a
distributed-column-control architecture reducing the burst-mode cycle
time, and a ringing-canceling output buffer ensuring reliable high-speed
data transfer
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International; 03/1995
-
T. Kaga,
Y. Sudoh,
H. Goto,
K. Shoji,
T. Kisu,
H. Yamashita,
R. Nagai,
S. Iijima,
M. Ohkura,
F. Murai,
T. Tanaka,
Y. Goto, N. Yokoyama,
M. Horiguchi,
M. Isoda,
T. Nishida,
E. Takeda
[show abstract]
[hide abstract]
ABSTRACT: In keeping with the trend of reducing DRAM cell area, with a
target for 1-gigabit DRAMs of less than 0.3 μm<sup>2</sup>, the
authors have developed a 0.29-μm<sup>2</sup> metal/insulator/metal
crown-shaped capacitor (MIM-CROWN) cell with low height by using
0.16-μm process technologies
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International; 01/1995
-
G. Kitsukawa,
M. Horiguchi,
Y. Kawajiri,
T. Kawahara,
T. Akiba,
Y. Kawase,
T. Tachibana,
T. Sakai,
M. Aoki,
S. Shukuri,
K. Sagara,
R. Nagai,
Y. Ohji,
N. Hasegawa, N. Yokoyama,
T. Kisu,
H. Yamashita,
T. Kure,
T. Nishida
[show abstract]
[hide abstract]
ABSTRACT: 256-Mb DRAM circuit technologies characterized by low power and
high fabrication yield for file applications are described. The newly
proposed and developed circuits are a self-reverse-biasing circuit for
word drivers and decoders to suppress the subthreshold current to 3% of
the conventional scheme, and a subarray-replacement redundancy technique
that doubles chip yield and consequently reduces manufacturing costs. An
experimental 256-Mb DRAM has been designed and fabricated by combining
the proposed circuit techniques and a 0.25-μm phase-shift optical
lithography, and its basic operations are verified. A 0.72-μm<sup>2
</sup> double-cylindrical recessed stacked-capacitor (RSTC) cell is used
to ensure a storage capacitance of 25 fF/cell. A typical access time
under a 2-V power supply voltage was 70 ns. With the proper device
characteristics, the simulated performances of the 256-Mb DRAM operating
with a 1.5-V power supply voltage are a data-retention current of 53
μA and an access time of 48 ns
IEEE Journal of Solid-State Circuits 12/1993; · 3.23 Impact Factor
-
G. Kitsukawa,
M Horiguchi,
Y. Kawaijiri,
T Kawahara,
T. Aikiba,
Y Kawase,
T Tachibana,
T Sakai,
M Aoki,
S. Shukuri,
K. Sagara,
R Nagai,
N Hasegawa, N Yokoyama,
T. Kisu,
H Yamashita,
T. Kure,
T Nishida
[show abstract]
[hide abstract]
ABSTRACT: The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25-μm CMOS technology with phase-shift lithography. It uses a 0.72-μm<sup>2</sup> RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International; 03/1993
