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S. Mayuzumi,
S. Yamakawa,
D. Kosemura,
M. Takei,
K. Nagata,
H. Akamatsu,
H. Wakabayashi,
K. Amari,
Y. Tateshita,
M. Tsukamoto,
T. Ohno,
A. Ogura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: An experimental study of mobility and velocity enhancement effects is reported for highly strained short-channel p-channel field-effect transistors (pFETs) using a damascene-gate process on Si (100) and (110) substrates. The relationship between the mobility and the saturation velocity of hole under a compressive stress over 2.0 GPa is discussed. The local channel stress of 2.4 GPa is successfully measured with ultraviolet-Raman spectroscopy for the 30-nm-gate-length device with top-cut compressive-stress SiN liner and embedded SiGe. Mobility and saturation-velocity enhancements of (100) substrate are larger than those of (110) under the high channel stress. In consequence, the saturation current on (100) is larger than that on (110) for the pFETs with higher channel stress and shorter gate length. Moreover, the large enhancement rate of saturation velocity to mobility by the uniaxial stress suggests high injection velocity for the pFETs with the stressors since the high channel stress is induced near the potential peak of the source by using the damascene-gate technology.
IEEE Transactions on Electron Devices 07/2010; · 2.32 Impact Factor
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ABSTRACT: This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.
IEEE Electron Device Letters 02/2010; · 2.85 Impact Factor
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ABSTRACT: A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 muA/mum at V<sub>ds</sub> = V<sub>gs</sub> = -1.0 V and I<sub>off</sub> = 100 nA/mum is achieved for the damascene-gate pFET with 0.3-mum channel width and 40-nm gate length.
IEEE Transactions on Electron Devices 12/2009; · 2.32 Impact Factor
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S. Mayuzumi,
S. Yamakawa,
D. Kosemura,
M. Takei,
K. Nagata,
H. Akamatsu,
K. Aamari,
Y. Tateshita,
H. Wakabayashi,
M. Tsukamoto,
T. Ohno,
M. Saitoh,
A. Ogura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: Mobility and velocity enhancements of hole on Si (110) and (100) substrates are accurately investigated for short-channel highly-strained pFETs. Local channel stress in short gate length is successfully observed for damascene gate pFETs with stressors by UV-Raman spectroscopy. A high channel stress of -2.4 GPa is measured for a 30-nm gate length device. Hole mobility and saturation velocity are precisely investigated for the -2.1 GPa stressed pFETs with a effective gate length of 30 nm. The mobility and velocity enhancements under high channel stress for (100) substrate are larger than those for (110). Therefore, saturation current on (100) is larger than that on (110) for pFETs with higher channel stress and shorter gate length.
VLSI Technology, 2009 Symposium on; 07/2009
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ABSTRACT: Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO<sub>2</sub> gate stacks with T<sub>inv</sub>=1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSi<sub>x</sub>/HfO<sub>2</sub> gate stacks with T<sub>inv</sub>=1.4 nm. High-performance n- and pFETs are achieved with I<sub>on</sub>=1300 and 1000 muA/mum at I<sub>off</sub> =100 nA/mum, V<sub>dd</sub>=1.0 V, and a gate length of 40 nm, respectively.
IEEE Transactions on Electron Devices 05/2009; · 2.32 Impact Factor
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S. Mayuzumi,
S. Yamakawa,
D. Kosemura,
M. Takei,
J. Wang,
T. Ando,
Y. Tateshita,
M. Tsukamoto,
H. Wakabayashi,
T. Ohno,
A. Ogura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.
VLSI Technology, 2008 Symposium on; 07/2008
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S. Mayuzumi,
J. Wang,
S. Yamakawa,
Y. Tateshita,
T. Hirano,
M. Nakata,
S. Yamaguchi,
Y. Yamamoto,
Y. Miyanami,
I. Oshiyama, [......],
R. Yamamoto,
S. Kanda,
K. Nagano,
H. Wakabayashi,
Y. Tagawa,
M. Tsukamoto,
H. Iwamoto,
M. Saito,
S. Kadomura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO<sub>2</sub> damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSi<sub>x</sub>/HfO<sub>2</sub> damascene gate stacks with Tinv =1.4 nm.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: A novel stress enhancement effect based on the damascene gate process with embedded SiGe (eSiGe) S/D for pFET is analyzed
in detail, using stress simulation and Ion measurement, for the first time. Removal of a dummy poly-Si gate eliminates the
repulsive force from the gate with a resulting enhancement of lateral compressive stress from eSiGe S/D. The stress enhancement
effect is proved by device fabrication and measurement. Furthermore, a new channel recess process is proposed and investigated.
Channel recess further increases stress at the channel. This effect is also confirmed by measurement, resulting in 14% current
enhancement.
11/2007: pages 109-112;
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J. Wang,
Y. Tateshita,
S. Yamakawa,
K. Nagano,
T. Hirano,
Y. Kikuchi,
Y. Miyanami,
S. Yamaguchi,
K. Tai,
R. Yamamoto, [......],
T. Kimura,
K. Kugimiya,
M. Tsukamoto,
H. Wakabayashi,
Y. Tagawa,
H. Iwamoto,
T. Ohno,
M. Saito,
S. Kadomura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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T Ando,
T Hirano,
K Tai,
S Yamaguchi,
K Tanaka,
I. Oshiyama,
M Nakata,
K Watanabe,
R Yamamoto,
S Kanda, [......],
H Wakabayashi,
Y Tagawa,
M Tsukamoto,
H Iwamoto,
M Saito,
S Toyoda,
H. Kumigashira,
M Oshima, N Nagashima,
S. Kadomura
[show abstract]
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ABSTRACT: The impacts of interfacial layer (IFL) thickness and crystallinity of HfO<sub>2</sub>/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSi<sub>x</sub>/HfO<sub>2</sub>) and pFETs (Ru/HfO<sub>2</sub>) including BTI. It was found that crystallization of HfO<sub>2</sub> causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO<sub>2</sub> thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO<sub>2</sub>/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500degC for the very first time.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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K. Tai,
T. Hirano,
S. Yamaguchi,
T. Ando,
S. Hiyama,
J. Wang,
Y. Nagahama,
T. Kato,
M. Yamanaka,
S. Terauchi,
S. Kanda,
R. Yamamoto,
Y. Tateshita,
Y. Tagawa,
H. Iwamoto,
M. Saito, N. Nagashima,
S. Kadomura
[show abstract]
[hide abstract]
ABSTRACT: We have developed a high performance pMOSFET with ALD-TiN/HfO<sub>2</sub> gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO<sub>2</sub> on (110) substrate (171 cm<sup>2</sup>/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO<sub>2</sub> on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at I <sub>off</sub> = 1 uA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO<sub>2</sub> gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+poly-Si/SiO<sub>2</sub> on (100) substrate
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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Y. Kikuchi,
Y. Tateshita,
T. Kataoka,
J. Wang,
Y. Miyanami,
K. Kugimiya,
T. Kimura,
T. Ikuta,
H. Ikeda,
S. Fujita,
R. Yamamoto,
S. Kanda,
Y. Tagawa,
H. Iwamoto,
T. Ohno,
T. Kobayashi,
M. Saito,
S. Kadomura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this epitaxy, ultra-shallow junctions (with effective junction depths (Xj,eff) under 9 nm@5E18) were formed, and 20-nm or shorter PMOS gate transistors were fabricated using the epitaxy
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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T. Hirano,
T. Ando,
K. Tai,
S. Yamaguchi,
T. Kato,
S. Hiyama,
Y. Hagimoto,
S. Takesako,
N. Yamagishi,
K. Watanabe,
R. Yamamoto,
S. Kanda,
S. Terauchi,
Y. Tateshita,
Y. Tagawa,
H. Iwamoto,
M. Saito,
S. Kadomura, N. Nagashima
[show abstract]
[hide abstract]
ABSTRACT: We propose HfSi<sub>x</sub>/HfO<sub>2</sub> gate stacks as the most suitable combination for high performance nMOSFETs. An equivalent work function (WF) to n<sup>+</sup>poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6 nm by low temperature process without using plasma nitridation both for metal and high-k fabrication. As a result, the extremely high drive current of 1.25mA/mum at off-state leakage of 1 nA/mum and low gate leakage current of 0.3A/cm<sup>2</sup> were obtained at Vdd = 1.3V with 65 nm gate length nMOSFETs without strain enhanced technology
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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Y. Takao,
H. Kudo,
J. Mitani,
Y. Kotani,
S. Yamaguchi,
K. Yoshie,
M. Kawano,
T. Nagano,
I. Yamamura,
M. Uematsu, N. Nagashima,
S. Kadomura
[show abstract]
[hide abstract]
ABSTRACT: This paper describes a 0.11 μm CMOS technology with
high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for
high performance and low power applications. Aggressive design rules,
0.11 μm gate transistor, and 2.2 μm<sup>2</sup> 6T-SRAM cell are
realized by using KrF 248 nm lithography, optical proximity-effect
correction (OPC), and gate-shrink techniques. Drain current of 0.63
mA/μm and 0.28 mA/μm are realized for nMOSFET and pMOSFET with
0.11 μm gate, respectively. Propagation delay of 2-input NAND with
the copper/hybrid VLK interconnects is estimated. The delay is improved
by more than 70%, compared to 0.18 μm CMOS technology with copper/FSG
interconnects
Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
