H.O. Johansson

Linköping University, Linköping, Östergötland, Sweden

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Publications (6)6.13 Total impact

  • H.O. Johansson, C. Svensson
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    ABSTRACT: Measurements have been done on a 0.8-µm CMOS sub-sampling circuit where a 16-Gbit/s data stream was successfully sampled. The input bit-rate was limited by the test setup. SPICE simulations on extracted layout with included bondwire inductances show correct sampling of 25-Gbit/s data streams. The circuit uses aggressively designed sampling switches and input pads. The package for the circuit is co-designed with the chip to attain high input-bandwidth.
    Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European; 10/1998
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    H.O. Johansson
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    ABSTRACT: We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified
    IEEE Journal of Solid-State Circuits 03/1998; · 3.06 Impact Factor
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    H.O. Johansson, C. Svensson
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    ABSTRACT: A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-μm transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-μm standard CMOS is 21 ps (~48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-μm standard CMOS process show successful sampling of every thirty second bit of a 5-Gb/s data stream
    IEEE Journal of Solid-State Circuits 03/1998; · 3.06 Impact Factor
  • H.O. Johansson
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    ABSTRACT: Successful sampling of every 32nd bit in a 7 Gbit/s data stream has been shown with a 0.8 μm CMOS circuit which is based on parallel sampling. The input bandwidth of the chip is the suspected bit rate limiting factor. The input bandwidth is mainly set by the wire characteristic impedance and the input capacitance of the chip. Half of a 5 Gbit/s data stream has been received by the same circuit. This indicates that (full) reception of 5 Gbit/s data-streams is possible. The bit rate limiting factor in this case is the accuracy and jitter of the control-clocks to the sampling-switches
    Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on; 01/1998
  • H.O. Johansson, Jiren Yuan, C. Svensson
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    ABSTRACT: The interconnects between chips are gaining in importance. We study a line-receiver to find out what is the limit of transmission speed onto a CMOS chip. The high tracking-speed of an NMOS sampling switch is used together with parallelism to attain high data-rates. 4 Gsamples/s sample-rate and 2 Gbit/s bit-rate (two samples per bit) has been shown experimentally with a 0.8 μm CMOS test-circuit. Single pulse measurements and simulations show that even higher rates are possible
    VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on; 07/1996
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    ABSTRACT: Implementing neural network hardware is a challenging task with tough requirements on computation and communication. We explore a time-multiplexed architecture with both bit-serial communication and computation, SINN (Serially Implemented Neural Network), for which the main goal is a high computation/area ratio. On-chip learning is excluded since this is a waste of hardware resources during run-time for many applications. Our experience is that an optimized bit-serial implementation has smaller area, while power consumption is increased, compared to a parallel structure
    ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International; 10/1994