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ABSTRACT: This paper describes the front-end architecture for a fully
integrated low-voltage CMOS video DSP function, including AGC,
equalization, clamping, sync, and A/D conversion. With multiple clock
domains and many high-activity pads, the large digital section of the IC
generates high levels of substrate and power line noise, which cannot be
avoided with quiet period sampling. The analog section is therefore
designed to minimize the injected noise by other circuit techniques. The
system maximizes the available dynamic range in the 3.3-V supply, with
several high-bandwidth rail-to-rail functions. A novel arrangement with
high noise immunity level estimators is used to clamp the video in the
middle of the dynamic range of the input amplifier, hence reducing
amplification of unwanted dc components. Extensive mixed signal test
facilities are also included in the design. The chip is fabricated in
0.5-μm CMOS, and operates from a single 3.3-V supply
IEEE Journal of Solid-State Circuits 08/1998; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: This paper describes the front-end architecture for a fully integrated low voltage CMOS video DSP function, including AGC, equalisation, clamping, sync and A/D conversion. Attention is paid to minimising the influence of substrate and power supply noise despite a large digital part with differing clock domains. The system maximises the available dynamic range in the 3.3V supply, with several high bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the AGC input, hence minimising the amplification of unwanted DC components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5µ CMOS, and operates from a single 3.3V supply.
Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European; 10/1997
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ABSTRACT: This paper describes the analog front-end of a fully integrated
CMOS TV decoder, suitable for the reception of terrestrial as well as
satellite signals, based on the D2-MAC transmission system. While the
video reconstruction is undertaken using DSP, the front-end subsystem
incorporates many linear and non-linear analog functions, including
amplitude measuring, AGC, clamping, data slicing, clock recovery and of
course, A/D conversion for the MAC signal processing. The chip is
fabricated in 1-μ CMOS, and operates from a single 5-V supply
IEEE Journal of Solid-State Circuits 09/1994; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with guiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-um CMOS, and operates from a single 3.3-V supply.
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[show abstract]
[hide abstract]
ABSTRACT: This paper describes the analog front-end of a fully integrated CMOS TV decoder, suitable for the reception of terrestrial as well as satellite signals, based on the D2-MAC transmission system. While the video reconstruction is undertaken using DSP, the front-end subsystem incorporates many linear and non-linear analog functions, including amplitude measuring, AGC, clamping, data slicing, clock recovery and of course, A/D conversion for the MAC signal processing. The chip is fabricated in 1-u CMOS, and operates from a single 5-V supply.
