M. Yamaguchi

Toshiba Corporation, Edo, Tōkyō, Japan

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Publications (8)3.02 Total impact

  • M. Tsukuda · I. Omura · Y. Sakiyama · M. Yamaguchi · K. Matsushita · T. Ogura
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    ABSTRACT: Critical N-base layer design in IGBT is discussed regarding electro-magnetic interference (EMI) and switching losses during turn-off. The newly proposed criteria for oscillation and avalanche induced loss were given by a simple equation model and the validity of the model has been confirmed with experimental results. This paper shows an efficient design method of N-base for EMI-free IGBT with considering the turn-off loss. In addition, EMI reduction structure with partly buried N layer in N-base was proposed for break through the design limit of N-base.
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
  • S Ono · W. Saito · M. Izumisawa · Y. Sumi · S. Kurushima · M. Tsuji · K. Tokano · M Yamaguchi
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    ABSTRACT: We investigated the profile dependency of specific on-resistance (R<sub>on</sub>A) under high- temperature and high-current-density conditions for 600 V-class semi-superjunction MOSFETs fabricated by the double-ion-implantation and multi-epitaxial method, for the first time. The column doping profile is an important design parameter for the R<sub>on</sub>A characteristics because the profile affects the electron mobility (mue) in the drift region. The n-column profile was modulated by the column diffusion time (t<sub>diff</sub>) in this experiment. The optimal t<sub>diff</sub> achieved minimal R<sub>on</sub>A under the high-temperature and high-current-density conditions.
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
  • W. Saito · T. Nitta · Y. Kakiuchi · Y. Saito · K. Tsuda · I. Omura · M. Yamaguchi
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    ABSTRACT: The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.
    IEEE Electron Device Letters 09/2007; 28(8-28):676 - 678. DOI:10.1109/LED.2007.901665 · 3.02 Impact Factor
  • W. Saito · M. Kuraguchi · Y. Takada · K. Tsuda · T. Domon · I. Omura · M. Yamaguchi
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    ABSTRACT: The current collapse phenomena in 380V/1.9A GaN power-HEMTs designed for high-voltage power electronics application is reported. The influence of these phenomena to the power-electronics circuit performance under high applied voltage is discussed using a 27.1 MHz class-E amplifier, which can be one of an industrial application candidate. It has been found that the optimized field plate structure minimizes the increase of conduction loss caused by the current collapse phenomena and thus improves the power efficiency of the circuit. The minimized device achieved the output power of 13.8 W and the power efficiency of 89.6 % for the demonstrated circuit even with the applied drain voltage of 330 V and the switching frequency of 27.1 MHz. These results show the nature possibility of a new GaN-device application with both high voltage and high frequency condition
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
  • M Yamaguchi · I. Omura · S. Urano · S. Umekawa · M Tanaka · T Okuno · T Tsunoda · T Ogura
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    ABSTRACT: The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dV<sub>CE</sub>/dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable V<sub>GE</sub> overshoot and the resultant uncontrollable dV<sub>CE</sub>/dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004
  • Source
    A. Nakagawa · T. Matsudai · T. Matsuda · M. Yamaguchi · T. Ogura
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    ABSTRACT: We have previously proposed and analyzed the MOSFET-mode operation of ultra-thin wafer PTIGBTs in (T. Matsudai et. al., Proc. of ISPSD'02, p.258). The present paper, for the first time, presents an analytical theory of MOSFET-mode operation, and shows that the safe operating area is determined by a mechanism similar to the second breakdown of npn bipolar transistors. The present paper also experimentally demonstrates, for the first time, that the MOSFET-mode IGBTs are strongly effective for soft switching applications. The developed MOSFET-mode 900 V 60 A thin wafer trench gate PTIGBTs have reduced turn-off loss by 55% at 125°C, compared with the conventional (4th generation) soft switching PTIGBTs.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004
  • M. Yamaguchi · I. Omura · S. Urano · T. Ogura
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    ABSTRACT: In this paper, a new design concept is proposed for 600V IGBTs to achieve both fast switching and unclamped inductive switching (UIS) capability. The concept is based on optimizing p-emitter efficiency (γ) for each condition of on-state and sustaining mode. Here the γ is reduced in on-state to lower the turn-off loss, but kept enough in sustaining mode to suppress the electric field. In particular, it is show that the γ of more than 0.4 in sustaining mode prevents the short-time UIS failure. The concept was successfully applied to NPT-IGBT, and the fabricated device has demonstrated fast switching adaptable to a frequency of 150 kHz and UIS capability of 28mJ/mm<sup>2</sup> at a high current density ( J<sub>C</sub>) of 200A/cm<sub>2</sub> (about 6 times the J<sub>C</sub> of MOSFETs).
    Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on; 05/2003
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    ABSTRACT: The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V<sub>CE</sub>(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V<sub>CE</sub>(sat). By numerical simulation, it has been confirmed that the trade-off relation between V<sub>CE</sub>(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V<sub>CE</sub>(sat) of 1.6 V at 180 A/cm<sup>2</sup> has been realized for the 600 V trench-gate NPT-IGBT
    Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on; 02/2000