M. Yamaguchi

Toshiba Corporation, Edo, Tōkyō, Japan

Are you M. Yamaguchi?

Claim your profile

Publications (17)12.49 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Four types of the field-plate (FP) structure were fabricated to discuss the relation between the current collapse phenomena and the electric-field peak in high-voltage GaN-HEMTs. The on -resistance increase caused by current collapse phenomena is dramatically reduced by the single-gate-FP and dual-FP structures compared with the source-FP structure, because the gate-edge electric field was reduced by the gate-FP electrode. The dual-FP structure was slightly more effective to suppress the collapse phenomena than the single-gate-FP structure, because the two-step FP structure relaxes the electric-field concentration at the FP edge. These results show that the gate-edge peak strongly affects the on -resistance modulation. Although the FP edge peak also causes the collapse phenomena, its influence is weak.
    IEEE Electron Device Letters 08/2010; · 2.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: High-voltage (> 400 V) GaN high-electron mobility transistors were fabricated using two types of heterostructures with different buffer layer structures. The buffer layer structure affected the crystal defect density in grown AlGaN/GaN heterostructure. The static on-resistance under low applied voltage was independent of the buffer layer structure because it has no influence on the 2-D electron-gas density. On the other hand, the drain leakage current through the grown layers and the dynamic on-resistance increase caused by the current collapse phenomena depended on the buffer layer structure. The leakage current was reduced by the AlN/n-GaN/AlN layers because of the potential barrier at the AlN/n-GaN interface and no-depletion of the n-GaN layer. In addition, the experimental results showed that the dynamic on-resistance was increased with the edge dislocation density and was not influenced by the screw dislocation density. From these results, it can be expected that edge dislocation is related to the electron trapping center, which must be reduced to suppress the current collapse phenomena.
    IEEE Transactions on Electron Devices 08/2009; · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The authors analyzed the surge voltage causing the oscillation in detail and found that the peak electric field at punch-through E<sub>P</sub> is proportional to the maximum surge voltage. The maximum surge voltage can be decreased by shifting the punch-through position W<sub>P</sub> toward the cathode side because the W<sub>P</sub> shift leads E<sub>P</sub> lowering. This dynamic punch-through design is applicable for whole operating condition. Based on the above discussions, a PIN-diode with a novel structure was invented that achieves the ideal carrier profile for shifting the W<sub>P</sub> closer to the cathode side with high electron injection during low-current operation. The simulation results show the maximum surge voltage causing oscillation was suppressed to about 50% lower and the switching loss of the diode also decreased to about 60% lower in the same time compared with the conventional structure.
    Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
  • [Show abstract] [Hide abstract]
    ABSTRACT: 600 V-class superjunction (SJ)-MOSFETs were developed using our original high-resolution Scanning Spread Resistance Microscopy (SSRM) analysis technology [1] for optimization of trench filling process for the first time. The SSRM analysis is a powerful tool for the SJ structure design, because it can be achieved the measurement of two- dimensional (2D)-carrier profile and detect of minute voids. The measured profile was applicable for device simulation of the SJ-Diode and the estimated breakdown voltage was in good agreement with the experimental values. By the feed back of these results to the trench filling process, the breakdown voltage was increased and the trade-off characteristics between the breakdown voltage and the specific on-resistance were achieved to 685 V/16.5 mOmegacm<sup>2</sup> in the fabricated SJ-MOSFET.
    Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
  • [Show abstract] [Hide abstract]
    ABSTRACT: Critical N-base layer design in IGBT is discussed regarding electro-magnetic interference (EMI) and switching losses during turn-off. The newly proposed criteria for oscillation and avalanche induced loss were given by a simple equation model and the validity of the model has been confirmed with experimental results. This paper shows an efficient design method of N-base for EMI-free IGBT with considering the turn-off loss. In addition, EMI reduction structure with partly buried N layer in N-base was proposed for break through the design limit of N-base.
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: We investigated the profile dependency of specific on-resistance (R<sub>on</sub>A) under high- temperature and high-current-density conditions for 600 V-class semi-superjunction MOSFETs fabricated by the double-ion-implantation and multi-epitaxial method, for the first time. The column doping profile is an important design parameter for the R<sub>on</sub>A characteristics because the profile affects the electron mobility (mue) in the drift region. The n-column profile was modulated by the column diffusion time (t<sub>diff</sub>) in this experiment. The optimal t<sub>diff</sub> achieved minimal R<sub>on</sub>A under the high-temperature and high-current-density conditions.
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: Suppression of the on-resistance modulation caused by the current collapse phenomena in the high-voltage GaN-HEMT was successful by using dual-field plate (FP) structure and back-side FP. A 480-V/2A GaN-HEMT was designed and fabricated for power electronic applications. In this device, the on-resistance modulation was negligible as low as 5% even under an applied voltage of 300 V. Boost converter circuit was demonstrated using the fabricated device with an output power of 54 W, high power efficiency of 92.7% and high switching frequency of 1 MHz.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q <sub>gd</sub> for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q <sub>gd</sub> / A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R <sub>on</sub> A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R <sub>on</sub> Q <sub>gd</sub> for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.
    IEEE Transactions on Electron Devices 09/2007; · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.
    IEEE Electron Device Letters 09/2007; · 2.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We report the experimental results detailed about the n-buffer layer (n-BAL: n-bottom assist layer) of 600 V-class semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (R<sub>on</sub>A) and the breakdown voltage (V<sub>B</sub>), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio T<sub>BAL</sub>-ratio and the doping concentration N<sub>BAL</sub> were varied in this work. As a result, the VB=750 V, the R<sub>on</sub>A=24.6 mOmegacm<sup>2</sup>, the maximum avalanche current density J<sub>AP</sub>=292 A/cm<sup>2</sup> (I<sub>AP</sub>=7.6A, E<sub>AS</sub>=1.25 J/cm<sup>2</sup>), and softness factor=0.277 were obtained with the structure of T<sub>BAL</sub>-ratio=27% and N<sub>BAL</sub>=1.0x10<sup>15</sup>cm<sup>-3</sup>. The demonstration results showed that NPT (non punch through)-type design (with high T<sub>BAL</sub>-ratio and high N<sub>BAL</sub>) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (punch through)-type design.
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents 12 V 10A 1 chip DC/DC converter IC based on the low cost 0.6 mum BiCD process. The chip adopted low impedance metal bump technology and a high speed gate driving technique for large LDMOS, what we call "distributed driver circuit". The fabricated chip achieves that the on resistance of 20 V output LDMOS is 9.7mOmega(@drain current=5A, gate voltage=5 V) and the maximum efficiency is 88.9% at output current 5A when the input voltage, the output voltage and switching frequency is 12 V, 1.3 V and 780 KHz, respectively.
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A 13.56-MHz class-E amplifier with a high-voltage GaN HEMT as the main switching device is demonstrated to show the possibility of using GaN HEMTs in high-frequency switching power applications such as RF power-supply applications. The 380-V/1.9-A GaN power HEMT was designed and fabricated for high-voltage power-electronics applications. The demonstrated circuit achieved the output power of 13.4 W and the power efficiency of 91% under a drain-peak voltage as high as 330 V. This result shows that high-voltage GaN devices are suitable for high-frequency switching applications under high dc input voltages of over 100 V.
    IEEE Electron Device Letters 06/2006; · 2.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The current collapse phenomena in 380V/1.9A GaN power-HEMTs designed for high-voltage power electronics application is reported. The influence of these phenomena to the power-electronics circuit performance under high applied voltage is discussed using a 27.1 MHz class-E amplifier, which can be one of an industrial application candidate. It has been found that the optimized field plate structure minimizes the increase of conduction loss caused by the current collapse phenomena and thus improves the power efficiency of the circuit. The minimized device achieved the output power of 13.8 W and the power efficiency of 89.6 % for the demonstrated circuit even with the applied drain voltage of 330 V and the switching frequency of 27.1 MHz. These results show the nature possibility of a new GaN-device application with both high voltage and high frequency condition
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
  • [Show abstract] [Hide abstract]
    ABSTRACT: The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dV<sub>CE</sub>/dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable V<sub>GE</sub> overshoot and the resultant uncontrollable dV<sub>CE</sub>/dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We have previously proposed and analyzed the MOSFET-mode operation of ultra-thin wafer PTIGBTs in (T. Matsudai et. al., Proc. of ISPSD'02, p.258). The present paper, for the first time, presents an analytical theory of MOSFET-mode operation, and shows that the safe operating area is determined by a mechanism similar to the second breakdown of npn bipolar transistors. The present paper also experimentally demonstrates, for the first time, that the MOSFET-mode IGBTs are strongly effective for soft switching applications. The developed MOSFET-mode 900 V 60 A thin wafer trench gate PTIGBTs have reduced turn-off loss by 55% at 125°C, compared with the conventional (4th generation) soft switching PTIGBTs.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004
  • M. Yamaguchi, I. Omura, S. Urano, T. Ogura
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a new design concept is proposed for 600V IGBTs to achieve both fast switching and unclamped inductive switching (UIS) capability. The concept is based on optimizing p-emitter efficiency (γ) for each condition of on-state and sustaining mode. Here the γ is reduced in on-state to lower the turn-off loss, but kept enough in sustaining mode to suppress the electric field. In particular, it is show that the γ of more than 0.4 in sustaining mode prevents the short-time UIS failure. The concept was successfully applied to NPT-IGBT, and the fabricated device has demonstrated fast switching adaptable to a frequency of 150 kHz and UIS capability of 28mJ/mm<sup>2</sup> at a high current density ( J<sub>C</sub>) of 200A/cm<sub>2</sub> (about 6 times the J<sub>C</sub> of MOSFETs).
    Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on; 05/2003
  • [Show abstract] [Hide abstract]
    ABSTRACT: The 600 V Non-Punch Through (NPT) IGBT which has low on-state voltage (V<sub>CE</sub>(sat)) has been developed. This device has a fine pitch trench-gate structure at the emitter side and the collector layer with low injection efficiency at collector side. A novel profile has been installed to realize low injection efficiency and low V<sub>CE</sub>(sat). By numerical simulation, it has been confirmed that the trade-off relation between V<sub>CE</sub>(sat) and turn-off loss of the trench-gate NPT-IGBT is as good as that of the trench-gate punch through (PT-)IGBT. Adopting the novel profile for the collector structure, the low V<sub>CE</sub>(sat) of 1.6 V at 180 A/cm<sup>2</sup> has been realized for the 600 V trench-gate NPT-IGBT
    Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on; 02/2000