-
[show abstract]
[hide abstract]
ABSTRACT: The objective of this paper is to clarify the principle of stabilization in flapping-of-wings flight of a butterfly, which is rhythmic and cyclic motion. For this purpose, a dynamics model of a butterfly is derived by Lagrangepsilas method, where the butterfly is considered as a rigid multi-body system. For the aerodynamic forces, a panel method is applied. Validity of the mathematical models is shown by agreement of the numerical result with the measured data. Then, periodic orbits of flapping-of-wings flights are searched in order to fly the butterfly models. Almost periodic orbits are obtained, but the model in the searched flapping-of-wings flight is unstable. This research, then, studies how the flexibly torsional wings effect on the flight stability. Numerical simulations demonstrate that the flexible torsion reduces the flight instability.
Automation Congress, 2008. WAC 2008. World; 11/2008
-
[show abstract]
[hide abstract]
ABSTRACT: A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has
been developed using a novel 3-stage-pipelined architecture. The
address-access path which is usually designed by analog means is
digitized, separated into three stages by latch circuits at the column
switch and data-out buffer. Since this architecture requires no
additional read/write bus and data amp, it minimizes an increase in die
size. Using the standardized GTL interface, a 250-Mbyte/s synchronous
DRAM with die size of 113.7-mm<sup>2</sup>, which is the same die size
as the conventional DRAM, has been achieved with 0.50-μm CMOS process
technology
IEEE Journal of Solid-State Circuits 05/1994; · 3.23 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: A 3.3 V 512 k×18×2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on; 06/1993
-
[show abstract]
[hide abstract]
ABSTRACT: Tunnelling through Tertiary mudstone bedrocks often encounters long-term instability in terms of high rock pressure or excessive displacement of tunnel walls. These deposits tend to soften due to water absorption upon unloading, moisture/humidity changes and weathering, and deteriorate with time. In this paper, strength deterioration due to softening of mudstone and its interaction to tunnel performance are briefly discussed; then, a finite element analysis is presented as an example for illustrating the influence of strength deterioration upon tunnel behaviour. Also described is stress transfer around tunnel associated with progressive yielding due to softening.
International Journal of Rock Mechanics and Mining Sciences.