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ABSTRACT: We report on spin transfer torque magnetoresistance random access memory (STT-MRAM) with magnetic tunnel junctions (MTJs) that have a top-pinned stacking structure. By adopting the top-pinned structure, in which a pinned layer and an antiferromagnetic layer are deposited above the MgO tunnel barrier, we can relieve the current limitation caused by driving power asymmetry of the transistor in a 1T/1M structure without an additional current path to make a reverse connection between the transistor and the top side of the MTJs, resulting in the cell area being reduced by about half.
VLSI Technology (VLSIT), 2010 Symposium on; 07/2010
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ABSTRACT: We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enables to reduce the threshold voltage (V<sub>th</sub>) fluctuation in nMOSFETs at high V<sub>d</sub> by 15%. We have clarified by direct carrier profiling and 3D simulation that the parallel implantation makes lateral extension edge smooth (less roughness induced by gate LER). Thanks to reduced fluctuation in effective channel length, we have made it possible to operate 20-nm nMOSFETs with the V<sub>th</sub> variability as much as pMOSFETs have.
VLSI Technology, 2009 Symposium on; 07/2009
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K. Ikeda,
T. Miyashita,
T. Kubo,
T. Yamamoto,
T. Sukegawa,
K. Okabe,
H. Ohta,
Y.S. Kim,
H. Nagai,
M. Nishikawa,
Y. Shimamune,
A. Hatada,
Y. Hayami,
K. Ohkoshi,
N. Tamura,
K. Sukegawa,
H. Kurata,
S. Satoh,
M. Kase, T. Sugii
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ABSTRACT: We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also performed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance bulk CMOS transistors with world competitive nFET and pFET drive currents of 1282/835 muA/mum at 100 nA/mum off-current at Vd = 1 V and Lg = 34 nm respectively, were developed with a conventional poly/SiON gate stack. The developed CMOS transistors not only have high-performance but also manufacturing friendly and cost effective compared with metal/high-k stack devices.
VLSI Technology, 2008 Symposium on; 07/2008
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ABSTRACT: We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner Teff are improved. On the other hand, unlike pMOS, Ni-FUSI process is not performed in nMOS. Both higher activation of halo and reduction of parasitic resistance in nMOSFET are improved by the combination of DCL structure and FLA in Ni-silicidation. Consequently, the higher drive currents of 1255 muA/mum and 759 muA/mum were obtained I<sub>off</sub>=122 nA/mum and 112 nA/mum at |<sub>Vdd</sub>|=1.0 V for nMOSFET and pMOSFET, respectively.
VLSI Technology, 2008 Symposium on; 07/2008
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H Kudo,
K Ishikawa,
M. Nakaishi,
A. Tsukune,
S Ozaki,
Y Nakata,
S Akiyama,
Y Mizushima,
M Hayashi,
Ade A. Akbar,
T Kouno,
H Iwata,
Y Iba,
T Ohba,
T. Futatsugi,
T Nakamura, T. Sugii
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ABSTRACT: Via cleaning using gas-phase organic acid has a high potential for improving the reduction capability of copper oxides (CuO), not degrading porous ultra-low-k dielectrics, and reducing processing cost. We applied our via cleaning technique to intermediate and semi-global levels consisting of homogeneous interlayer dielectric architectures based on the 45-nm technology node. The CuO reduction rate was by a factor of 10, which was much higher compared with that using hydrogen. This allowed us to achieve a 100% yield for a mega-scaled via chain. Via chains treated with gas-phase organic acid also showed greater resistance against stress-induced voiding. In addition, we substantially reduced the via cleaning process cost by a factor of 10 compared with the cost of conventional wet chemical cleaning. In addition, organic acid is preferable because it occurs naturally and is thus ecologically friendly.
Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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H. Kudo,
M. Haneda,
T. Tabira,
M. Sunayama,
N. Ohtsuka,
N. Shimizu,
H. Ochimizu,
A. Tsukune,
T. Suzuki,
H. Kitada,
S. Amari,
H. Matsuyama,
T. Owada,
H. Watatani,
T. Futatsugi,
T. Nakamura, T. Sugii
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ABSTRACT: To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.
Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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ABSTRACT: This paper review our developed junction profile engineering technique that uses millisecond annealing (MSA): MSA is implemented prior to spike- RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower MSA temperatures with wide process window because of its low sensitivity to MSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45 nm node low standby power (LSTP) CMOS technology (K. Sukegawa et al., 2007) as well as the high performance technology (T. Yamamoto et al., 2007), and achieved the competitive performance of CMOS devices thanks to the reduction in the source- drain extension (SDE) resistance for pMOSFETs and the effective halo profile formation of nMOSFETs.
Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on; 06/2008
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K. Ikeda,
T. Miyashita,
H. Ohta,
Y.S. Kim,
M. Fukuda,
Y. Shimamune,
N. Tamura,
H. Fukutome,
A. Hatada,
K. Okabe,
Y. Hayami,
M. Tajima,
H. Morioka,
J. Ogura,
K. Kawamura,
H. Kurata,
K. Sukegawa,
S. Satoh,
M. Kase, T. Sugii
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ABSTRACT: Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process window that comprehensively optimizes both channel strain, induced by eSiGe-S/D (proximity, elevated height, and uniformity), and carrier profiles (offset spacer and thermal budget including millisecond annealing). An optimized eSiGe-S/D with a low thermal budget and amorphous Si gate decreases electrical fluctuations resulting in continuous scaling and a lower manufacturing cost.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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H. Ohta,
N. Tamura,
H. Fukutome,
M. Tajima,
K. Okabe,
A. Hatada,
K. Ikeda,
K. Ohkoshi,
T. Mori,
K. Sukegawa,
S. Satoh, T. Sugii
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ABSTRACT: A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesn't require any additional capping layers used in SMT. DCL fabricated directly on the gate dielectric film effectively improved drive currents without degrading short channel immunity because DCL technique dose not affect halo, extension and source/drain (S/D) profiles. The higher dopant concentration in DCL resulted in both the better electron mobility and the thinner equivalent oxide thickness of inversion layer capacitance (T<sub>eff</sub>). Consequently, the higher drive currents of 1204 muA/mum and 786 muA/mum were obtained at V<sub>dd</sub>=1.0 V for nMOSFET and pMOSFET, respectively.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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H. Kudo,
M. Haneda,
H. Ochimizu,
A. Tsukune,
S. Okano,
N. Ohtsuka,
M. Sunayama,
H. Sakai,
T. Suzuki,
H. Kitada,
S. Amari,
T. Tabira,
H. Matsuyama,
N. Shimizu,
T. Futatsugi, T. Sugii
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ABSTRACT: We successfully encapsulated Cu wiring with an ultra-thin self-forming barrier consisting of MnO and a bi-layer of MnO/Ta. TDDB test showed that the ILDs lifetime increased by a factor of 100 over that of our control sample. The encapsulated Cu wiring increased EM lifetime by a factor of more than 47. For via chains that are vulnerable to thermal stress, the encapsulated Cu wiring showed no SIV failure. The resistance of the encapsulated Cu wiring was 13% lower than that of the control sample. We expect encapsulated Cu wiring to have greater endurance to the electrical and thermal stresses for use in 32-nm nodes and beyond.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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T. Yamamoto,
T. Kubo,
T. Sukegawa,
E. Takii,
Y. Shimamune,
N. Tamura,
T. Sakoda,
M. Nakamura,
H. Ohta,
T. Miyashita,
H. Kurata,
S. Satoh,
M. Kase, T. Sugii
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ABSTRACT: We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the I<sub>on</sub> of 33-nm CMOS devices (8.2% / 12.8% with an I<sub>off</sub> = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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T. Miyashita,
K. Ikeda,
Y.S. Kim,
T. Yamamoto,
Y. Sambonsugi,
H. Ochimizu,
T. Sakoda,
M. Okuno,
H. Minakata,
H. Ohta, [......],
T. Mori,
A. Hasegawa,
H. Kurata,
K. Sukegawa,
A. Tsukune,
S. Yamaguchi,
M. Kase,
T. Futatsugi,
S. Satoh, T. Sugii
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ABSTRACT: We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum<sup>2</sup>. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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K. Sukegawa,
T. Yamamoto,
H. Kudo,
T. Kubo,
T. Sukegawa,
H. Ehara,
H. Ochmizu,
M. Fukuda,
Y. Mizushima,
Y. Shimoda, [......],
H. Sakai,
A. Asneil,
S. Sakai,
H. Matsuyama,
H. Kurata,
A. Tsukune,
N. Shimrzu,
S. Satoh,
M. Kase, T. Sugii
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ABSTRACT: We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at V<sub>d</sub>=1.2 V are 0.54 mA/um at I<sub>off</sub>=40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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ABSTRACT: We have developed a novel junction profile engineering using thin sidewall structure and applied it to sub-40 nm uniaxial strained CMOS devices. This transistor used a high-k thin sidewall with electrical charge in achieving a higher drive current with keeping the short channel effect. Consequently, the 18.5/15.6% reduction of parasitic resistance achieve the 8.2/13.0% improvement in the saturation current (I<sub>on</sub>) at 38 nm gate length for nMOS and pMOS. In addition, I<sub>on</sub> dependence on active width (W<sub>g</sub>) for pMOS is very small. In the size of active width : 0.1 mum, a 42% of I<sub>on</sub> enhancement gave us I<sub>on</sub> = 680 muA/mum at V<sub>dd</sub>=1 V. These characteristics are originated from formation of inversion layer and suppressing channeling penetration of pocket impurities implanted. A high performance Bulk nMOS and pMOS were demonstrated with I<sub>on</sub> of 1069 muA/mum and 725 muA/mum at V<sub>dd</sub>=1 V / I<sub>off</sub>=100 nA/mum, respectively.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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T. Yamamoto,
T. Kubo,
T. Sukegawa,
A. katakami,
Y. Shimamune,
N. Tamura,
H. Ohta,
T. Miyashita,
S. Sato,
M. Kase, T. Sugii
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ABSTRACT: We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (I<sub>on</sub>) for PMOS / NMOS, and I<sub>on</sub> = 750(P) / 1030(N) [muA/mum] for I<sub>off</sub> = 100 [nA/mum] at V<sub>dd</sub>= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.
VLSI Technology, 2007 IEEE Symposium on; 07/2007
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ABSTRACT: We have developed a carbon (C) co-implantation technology that enables drastic improvement of Vth rolloff in nMOSFET having phosphorus (P) extension while maintaining the current drive, and reduces the extension sheet resistance in pMOSFET having boron (B) extension. The data revealed that C introduced into the extension region suppresses the P-extension tail for nMOSFET and improves B activation ratio for pMOSFET. We also found that combination of C and indium (In) pocket plays an important role for Vth rolloff improvement in nMOSFET.
Junction Technology, 2007 International Workshop on; 07/2007
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H. Kudo,
H. Ochimizu,
A. Tsukune,
S. Okano,
K. Naitou,
M. Sakamoto,
S. Takesako,
T. Shirasu,
A. Asneil,
N. Idani, [......],
Y. Mizushima,
H. Matsuyama,
Y. Suzuki,
N. Shimizu,
K. Yanai,
M. Nakaishi,
T. Futatsugi,
I. Hanyu,
T. Nakamura, T. Sugii
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ABSTRACT: According to the 45 nm BEOL technology node, we demonstrated that a homogeneous interlayer dielectric with dielectric constant of 2.25 has a substantial advantage in terms of RC delay reduction compared to other potential architectures such as hybrid and tri-level dielectrics. Combination of the homogeneous interlayer dielectric and ultra-thinned barrier metal lowered the RC delay to 86 % compared to that listed in the ITRS 2006 update.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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K. Sukegawa,
M. Okuno,
H. Ochimizu,
M. Yamaji,
M. Fukuda,
Y. Sanbonsugi,
H. Kudo,
E. Yoshida,
Y. Mizushima,
T. Arita, [......],
T. Watanabe,
T. Shirasu,
M. Kojima,
H. Kurata,
A. Tsukune,
K. Ikeda,
T. Futatsugi,
S. Satoh,
M. Kase, T. Sugii
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ABSTRACT: A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasized that this technology is cost-effective.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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ABSTRACT: The authors proposes a characteristic current (I_chr) to replace the conventional saturation drive current used to estimate approximate CMOS inverter delay times for deeply scaled devices. The authors also present a new device design method based on I_chr to achieve a higher operation frequency for CMOS inverter circuits. The new method shortens propagation delay time (Tpd) by 15%
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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Y.S. Kim,
Y. Shimamune,
M. Fukuda,
A. Katakami,
A. Hatada,
K. Kawamura,
H. Ohta,
T. Sakuma,
Y. Hayami,
H. Morioka,
J. Ogura,
T. Minami,
N. Tamura,
T. Mori,
M. Kojima,
K. Sukegawa,
K. Hashimoto,
M. Miyajima,
S. Satoh, T. Sugii
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ABSTRACT: The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
