M J Tsai

Publications (61)75.19 Total impact

• Conference Proceeding: Ti/HfO2 based RRAM operation voltage scaling for embedded memory

  C. H. Tsai, F. T. Chen, H. Y. Lee, Y. S. Chen, K. H. Tsai, T. Y. Wu, S. Z. Rahaman, P. Y. Gu, W. S. Chen, P. S. Chen, Z. H. Lin, P. L. Tseng, W. P. Lin, C.H. Lin, S. S. Sheu, M. -J. Tsai, T. K. Ku
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  ABSTRACT: Consumer gadgets make up the fastest growing market for electronic devices today. These products will rely more and more on embedded storage-type memory, which can store system and processing data without impacting standby power consumption. For embedded memory applications, including microcontrollers, automotive, and mobile code storage applications, NOR flash is a popular choice for its non-volatility and fast read time on the order of nanoseconds. However, its operation voltage is larger than 10V, and the write speed exceeds 10 microseconds. Although increasing density is not a key requirement for process scaling of embedded memory down to advanced nodes, the operation voltage needs to be reduced to continually lower power consumption and to match foundry offerings in the logic and mixed-signal sectors, both in the core voltages and the I/O voltages. Resistive random-access memory (RRAM) is proposed to be such a scalable embedded memory technology. RRAM offers the advantages of CMOS process compatibility, high speed, high endurance, low-voltage operation, and high cell density. In this article, we demonstrate that the operation voltage can be reduced to under 1V in the Ti/HfOx RRAM system with a multi-level RESET operation strategy, while keeping the write speed to less than 2 microseconds, opening up opportunities for RRAM in embedded memory applications.
  China Semiconductor Technology International Conference (CSTIC) 2013; 03/2013
• Source

  Available from: S. Z. Rahaman

  Article: Repeatable unipolar/bipolar resistive memory characteristics and switching mechanism using a Cu nanofilament in a GeOx film

  S. Z. Rahaman, S. Maikap, W. S. Chen, H. Y. Lee, F. T. Chen, M. J. Kao, M. J. Tsai
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  ABSTRACT: This paper investigates the repeatable unipolar/bipolar resistive switching memory characteristics in a copper/germanium-oxide/tungsten (Cu/GeOx/W) structure. The switching mechanism occurs because of the lower barrier height for hole injection rather than electron injection. Therefore, Cu ions, as a positive charge, migrate before initiating growth at the GeOx/W interface and dissolving at the GeOx/Cu interface. The diameter of the Cu nanofilament increases linearly from 0.13 Å to 25 nm as current compliances increase from 1 nA to 10 mA, as calculated using the other approach. The crystalline Cu nanofilament was also confirmed by high-resolution transmission electron microscopy analysis under SET. Good data retention with high resistance ratios of 102–105 (and >104 at 85 °C) and ∼109 was obtained under the bipolar and unipolar modes, respectively. Therefore, a maximum memory size of 5000 Pbit/in2 can be designed in the future.
  Applied Physics Letters 08/2012; 101(7):073106. · 3.84 Impact Factor
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Repeatable bipolar resistive switching with both polarity dependent SET/RESET scenario using Al/Cu/Ge0.2Se0.8/W structure

  S. Z. Rahaman, S. Maikap, H. Y. Lee, W. S. Chen, F. T. Chen, M.-J. Kao, M.-J. Tsai
  221st ECS Meeting, Seattle, WA; 05/2012
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Excellent resistive switching memory: Influence of GeOx in WOx mixture

  S. Z. Rahaman, S. Maikap, W. S. Chen, T. C. Tien, H. Y. Lee, F. T. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Influence of GeOx layer on resistive switching memory performance in a simple and CMOS compatible W/WOx/GeOx:WOx mixture/W structure has been investigated for the first time. All layers are confirmed by both HRTEM and XPS. This memory device has enhanced performance in terms of the resistance ratio, uniformity, and program/erase cycles as compared to W/WOx/W structure. An excellent read endurance and program/erase cycles of >;10^6 at large Vread of ±1V are obtained. Furthermore, the memory device exhibits robust data retention at 85°C. This device can be operated as low current as 0.1 μA.
  VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on, Hsinchu, Taiwan; 04/2012
• Source

  Available from: S. Z. Rahaman

  Article: Impact of TaOx nanolayer at the GeSex/W interface on resistive switching memory performance and investigation of Cu nanofilament

  S. Z. Rahaman, S. Maikap, W. S. Chen, H. Y. Lee, F. T. Chen, T. C. Tien, M. J. Tsai
  Journal of Applied Physics 03/2012; 111(6):063710. · 2.17 Impact Factor
• Article: Phase-Change Memory Devices Operative at 100

  K.F. Kao, Y.C. Chu, F.T. Chen, M.J. Tsai, T.S. Chin
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  ABSTRACT: Phase-change memory (PCM), although promising operative at room temperature, is struggling to achieve ten-year data retention over 100°C. We disclose here that a PCM device made of the composition Ga₂₅Te₈Sb₆₇ exhibits normal operation at 100°C for an endurance of at least 3 × 10⁵ cycles. At room temperature, the endurance is at least 5 × 10⁶ cycles. The set-reset speed of the devices reaches 20 ns, and the reset current is around 20% less than that of our reference test cells made of the benchmark Ge₂Sb₂Te₅.
  IEEE Electron Device Letters 09/2010; · 2.85 Impact Factor
• Article: Low power design of phase-change memory based on a comprehensive model

  M.-H. Chiang, Y.-B. Liao, J.-T. Lin, W.-C. Hsu, C. Yu, P.-C. Chiang, Y.-Y. Hsu, W.-H. Liu, S.-S. Sheu, K.-L. Su, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: In this study, the authors propose non-conventional phase-change memory programming schemes using a comprehensive model, which integrates the underlying electrical and thermal theories. Various pulsing schemes aiming to reduce operation power without compromising performance are assessed based on a calibrated model. Our results suggest that optimisation of power consumption can be done simply by design of pulsing techniques.
  IET Computers & Digital Techniques 08/2010; · 0.45 Impact Factor
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Low current bipolar resistive switching memory using CU metallic filament in Ge0.2Se0.8 solid-electrolyte

  S.Z. Rahaman, S. Maikap, C.-H. Lin, P.-J. Tzeng, H. Y. Lee, T.-Y. Wu, Y.-S. Chen, F. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Low current/voltage (1 nA/1.3V) operation of resistive switching memory device using Cu metallic filament in Ge0.2Se0.8 solid-electrolyte has been investigated. This resistive memory device have a large resistance ratio of > 10 at 1 nA current compliance, good endurance of ~10^5 cycles, and good data retention with a current of 1 nA up to 2×10^3 seconds. The low resistance state decreases with increasing the programming current from 1 nA to 500 μA, which can be useful for future nanoscale MLC applications. A strong Cu metallic filament is investigated by monitoring the negative erase current (Ie).
  VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on, Hsinchu, Taiwan; 04/2010
• Source

  Available from: S. Z. Rahaman

  Article: Bipolar resistive switching memory using cu metallic filament in Ge0.4Se0.6 solid electrolyte

  S. Z. Rahaman, S. Maikap, H.-C. Chiu, C.-H. Lin, T.-Y. Wu, Y.-S. Chen, P.-J. Tzeng, F. Chen, M.-J. Kao, M.-J. Tsai
  Electrochemical and Solid-State Letters 03/2010; 13(5):H159-H162. · 2.00 Impact Factor
• Article: Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti Cap

  H.Y. Lee, Y.S. Chen, P.S. Chen, T.Y. Wu, F. Chen, C.C. Wang, P.J. Tzeng, M.-J. Tsai, C. Lien
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  ABSTRACT: The memory performance of hafnium oxide (HfO_x)-based resistive memory containing a thin reactive Ti buffer layer can be greatly improved. Due to the excellent ability of Ti to absorb oxygen atoms from the HfO_x film after post-metal annealing, a large amount of oxygen vacancies are left in the HfO_x layer of the TiN/Ti/HfO_x/TiN stacked layer. These oxygen vacancies are crucial to make a memory device with a stable bipolar resistive switching behavior. Aside from the benefits of low operation power and large on/off ratio (>100), this memory also exhibits reliable switching endurance (>10⁶ cycles), robust resistance states (200??C), high device yield (~100%), and fast switching speed (<10 ns).
  IEEE Electron Device Letters 02/2010; · 2.85 Impact Factor
• Conference Proceeding: Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

  Y.S. Chen, H.Y. Lee, P.S. Chen, P.Y. Gu, C.W. Chen, W.P. Lin, W.H. Liu, Y.Y. Hsu, S.S. Sheu, P.C. Chiang, W.S. Chen, F.T. Chen, C.H. Lien, M.-J. Tsai
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  ABSTRACT: A 30×30 nm² HfO_x resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 10⁶ cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (R_HIGH) and low resistance (R_LOW) are proposed for the array to ensure a good operation window. A thin AlO_x buffer layer under the HfO_x layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program (PGM)/erase (ERS) disturb immunity.
  Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Low current (5 pA) resistive switching memory using high-к Ta2O5 solid electrolyte

  S. Maikap, S.Z. Rahaman, T.Y. Wu, F. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Bipolar resistive switching memory device using high-kappa Ta₂O₅ solid electrolyte in a Cu/Ta₂O₅/W structure with the device sizes from 0.2-8 mum was investigated. This resistive memory device has a high threshold voltage of 0.75 V, high resistance ratio (R_High/R_Low) of 3times10³, good endurance of > 10³, and excellent retention at 150degC. The memory device with a low current operation of 5 pA is obtained, for the first time, owing to the Cu metallic chain formation in the high-kappa Ta₂O₅ solid electrolyte. The strong Cu chain formation is also confirmed by monitoring both the negative voltage and current observations. The low resistance state (R_Low) decreases with increasing the current compliance from 5 pA to 700 muA, which can be useful for future multi-level data storage applications.
  Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Low Power Operation of Resistive Switching Memory Device Using Novel W/Ge0.4Se0.6/Cu/Al Structure

  S.Z. Rahaman, S. Maikap, H.C. Chiu, C.-H. Lin, T.-Y. Wu, Y.-S. Chen, P.-J. Tzeng, F. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Bipolar resistive switching memory device with a low power operation (200 muA/1.3 V) in a W/Ge_0.4Se_0.6/Cu/Al structure has been investigated. A stronger Cu chain formation can be observed by monitoring both the erase voltage and current. The low resistance state (R_Low) decreases with increasing the programming current from InA to 500 muA, which can be useful for multi-level of data storage. This resistive memory device has a large threshold voltage of ~0.5 V, good resistance ratio (R_High/R_Low) of 1.6 times 10², good endurance of >1.5 times 10⁵ cycles, and excellent retention (>11 hours) with a resistance ratio of > 1.3 times 10² at 150degC can be used in future nonvolatile memories.
  Memory Workshop, 2009. IMW '09. IEEE International; 06/2009
• Source

  Available from: S. Z. Rahaman

  Conference Proceeding: Low current and voltage resistive switching memory device using novel Cu/Ta2O5/W structure

  S.Z. Rahaman, S. Maikap, C.-H. Lin, T.-Y. Wu, Y.S. Chen, P.-J. Tzeng, F. Chen, C.S. Lai, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Low current/voltage (~10 nA/1.0V) resistive switching memory device in a Cu/Ta₂O₅/W structure has been proposed. The low resistance state (R_Low) of the memory device decreases with increasing the programming current from 10 nA to 1 mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (R_High/R_Low) of 5.3times10⁷, good endurance of >10³ cycles, and excellent retention (>11 hours) with resistance ratio of > 9times10³ can be useful in future non-volatile memory applications.
  VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009
• Conference Proceeding: Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM

  H.Y. Lee, P.S. Chen, T.Y. Wu, Y.S. Chen, C.C. Wang, P.J. Tzeng, C.H. Lin, F. Chen, C.H. Lien, M.-J. Tsai
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  ABSTRACT: A novel HfO₂-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>10⁶ cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: Snapback and overprogramming modeling using finite-element electrothermal simulation

  F. Chen, J.-T. Yeh, D.-S. Chao, Y.-C. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: We present a new model for the simulation of negative differential resistance (¿snapback¿) in a phase-change memory cell using an electrothermal finite-element iterative calculation implemented in ANSYS. This model improves upon our previous models by applying a double Arrhenius temperature-dependent resistivity for the amorphous chalcogenide, and a JMAK (n=3.5) model to describe the phase-change kinetics. As a result, the model captures the possibility of partial crystallization during typical pulsed heating conditions, a crucial factor in determining the abruptness of snapback. In addition to fitting our experimental data, the model is capable of predicting and characterizing the onset of overprogramming. Overprogramming occurs when the process of crystallizing some parts of the initially amorphous region leads to other parts heating above the melting point, leading to a remnant amorphous portion that limits the reduction of the cell¿s resistance. The paper also explores the impact of initial amorphous size as well as the presence of a defect breaking the symmetry of the amorphous hemisphere.
  Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual; 12/2008
• Conference Proceeding: High Endurance Multi-gate TiN Nanocrystal Memory Devices with High-k Blocking Dielectric and High Work Function Gate Electrode

  C.-P. Lu, C.K. Luo, B.Y. Tsui, C H Lin, P.J. Tzeng, C C Wang, H.Y. Lee, D.Y. Wu, M J Tsai
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  ABSTRACT: In this work, n-channel Multi-gate FET TiN nanocrystal memory using p⁺ poly-Si gate and Al₂O₃ high-k blocking dielectric is demonstrated with good transistor characteristics and moderate high memory window for the first time. High endurance of only 3% window narrowing after 10⁴ P/E cycles is demonstrated. The phenomenon and mechanism of erasing-first induced retention degradation are also reported.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: Highly Thermally Stable and Reproducible of ALD RuO2 Nanocrystal Floating Gate Memory Devices with Large Memory Window and Good Retention

  S. Maikap, W. Banerjee, P.-J. Tzeng, T.-Y. Wang, C.H. Lin, T.C. Tien, L.S. Lee, J.-R. Yang, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: Highly thermally stable (~1000degC) and reproducible of ALD RuO₂ nanocrystal floating gate memory devices with a large hysteresis memory window of DeltaV ap 14.6 V under a gate voltage of plusmn10 V have been observed. The memory window of DeltaV ap 4.2 V under a small gate voltage of plusmn3 V is also observed. Both program and erase speeds of DeltaV_FB>1 V@100 mus are achieved under Fowler-Nordheim injections. Excellent endurance of DeltaV ap 8.5V, before and after 10⁴ cycles and a large memory window of DeltaV ap 4.9 V after 10 years of retention (9% charge loss at 20degC and -20% charge loss at 85degC) are obtained. The high-performance ALD RuO₂ nanocrystal flash memory devices can be operated below 5 V.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
• Conference Proceeding: RESET-Enhancing Features for Via-Heated Phase-Change Memory Cells

  F.T. Chen, J.-T. Yeh, D.-S. Chao, M.-J. Chen, P. Yen, C.-M. Lee, J.-W. Chen, W.-S. Chen, M.-J. Kao, M.-J. Tsai
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  ABSTRACT: The various means of improving the performance of phase-change memory cells are reviewed. Simulation predictions are compared with experimental results. Emphasis is placed on RESET current reduction by considering the balance between Joule heating input and heat loss to surroundings. For a given via design rule, the double-confined structure gives the best overall performance to date. We attribute this to the low thermal conductivity of the phase-change material.
  VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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  Available from: itri.org.tw

  Article: Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer

  Ping-Hung Tsai, Kuei-Shu Chang-Liao, Chu-Yung Liu, Tien-Ko Wang, P.J. Tzeng, C.H. Lin, L.S. Lee, M.-J. Tsai
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  ABSTRACT: Operation properties of polysilicon-oxide-nitride-oxide-silicon-type Flash device with HfAlO charge-trapping layer having various Al contents were investigated in this letter. Satisfactory performance in terms of operation speed, retention, and program/erase endurance of the Flash device is achieved with the optimal Al content of 18%-28% in the HfAlO trapping layer. In addition, high-speed operation can be attained with the combination of channel-hot-electron-injection programming and band-to-band hot hole erasing for NOR architecture applications.
  IEEE Electron Device Letters 04/2008; · 2.85 Impact Factor