M.-J. Tsai

Industrial Technology Research Institute, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (101)107.17 Total impact

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    ABSTRACT: The device size-dependent resistive memory switching and improvement in the switching performance in a CMOS compatible W/TiN contact device is reported as compared to W/W, Al/TiN, and Ir/TiN contacts, due to oxygen-rich layer formation at the W/filament interface. A small device area of 0.15 × 0.15 μm $^{2}$ and interface between the electrodes has been observed from the transmission electron microscopy images. The fabricated small size devices have shown improved switching endurance with a small current compliance of 50 μA without separate forming process. The reactivity of electrode materials and its interface play an important role in obtaining the stable resistive switching behavior in W/TiN contact-formed W/TiO$_{x}$/TiN structure. This device has shown long consecutive switching cycles (>10$^{3}$), read endurance of >10$^{5}$ times, good uniformity, and data retention of >10 $^{4}$ s at 85 °C under low-current compliance of 50 μA.
    IEEE Transactions on Nanotechnology 05/2014; 13(3):409 - 417. · 1.80 Impact Factor
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    ABSTRACT: The dependence of resistive switching of ${rm Ta}/{rm TaO}_{rm X}/{rm HfO}_{rm X}$ device governed by general filamentary or novel defects-trapping mechanism on the operation current is demonstrated in this letter. The device with stable resistive switching, high nonlinearity, and robust self-compliance ${sim}{rm 1}~mu{rm A}$ is demonstrated, which can be integrated in the vertical RRAM structure. Based on constant current density switching $({sim}{rm 10^{3}}~{rm A}/{rm cm}^{2})$ governed by defects-trapping transport, where the low and high resistance states attributed to the resistance of ${rm Ta}/{rm TaO}_{rm X}$ layer and device initial state, the switching current reduction by scaling down the cell size is proposed in transition metal oxide RRAM.
    IEEE Electron Device Letters 01/2014; 35(2):202-204. · 2.79 Impact Factor
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    ABSTRACT: The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current ($I_{CELL}$) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference ( $V_{BE}$) of VPBJT, we propose a temperature-aware bitline (BL) voltage bias $(V_{BL-R})$ (TABB) scheme to provide current-mode sensing with 4.7× larger $I_{CELL}$ and 1.6× faster read speeds. Test results of fabricated 0.18 µm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware $V_{BL-R}$, resulting in sub-5-ns random read access times.
    IEEE Journal of Solid-State Circuits 01/2014; 49(4):908-916. · 3.06 Impact Factor
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    ABSTRACT: 1T-1R Zr/HfOx RRAM with improved uniformity is proposed, which is due to the easily Oxidation of Zr layer from both HfOx and supporting SiO2. The formation of ZrOx become a good current limiter which help the device prevent scalability issue.
    VLSI Technology, Systems, and Applications, 2013 International Symposium; 04/2013
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    ABSTRACT: Consumer gadgets make up the fastest growing market for electronic devices today. These products will rely more and more on embedded storage-type memory, which can store system and processing data without impacting standby power consumption. For embedded memory applications, including microcontrollers, automotive, and mobile code storage applications, NOR flash is a popular choice for its non-volatility and fast read time on the order of nanoseconds. However, its operation voltage is larger than 10V, and the write speed exceeds 10 microseconds. Although increasing density is not a key requirement for process scaling of embedded memory down to advanced nodes, the operation voltage needs to be reduced to continually lower power consumption and to match foundry offerings in the logic and mixed-signal sectors, both in the core voltages and the I/O voltages. Resistive random-access memory (RRAM) is proposed to be such a scalable embedded memory technology. RRAM offers the advantages of CMOS process compatibility, high speed, high endurance, low-voltage operation, and high cell density. In this article, we demonstrate that the operation voltage can be reduced to under 1V in the Ti/HfOx RRAM system with a multi-level RESET operation strategy, while keeping the write speed to less than 2 microseconds, opening up opportunities for RRAM in embedded memory applications.
    China Semiconductor Technology International Conference (CSTIC) 2013; 03/2013
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    ABSTRACT: The voltage ramping rate during the forming and set-reset process is strongly related to the formation of soft-breakdown (SBD) paths. In this paper, we examined the effect of two different operation methods in RRAM, including sweep and pulse modes. The RTN analysis has been utilized to examine their influences on the SBD paths. For the first time, we found a different behavior of the RTN currents generated by two different modes of operation. Results show that more SBD paths are created during the pulse mode which led to the instability of switched resistance, and induced the erratic bit during the readout of RRAM.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: Improved resistive switching memory characteristics in a novel W/TaOx/TiOxN/TiN device with a small current compliance of 50 μA have been investigated. Memory device has shown consecutive repeatable resistive switching cycles (>102) with small operation voltage of ±1.5V. The device with TaOx/TiOxN shows improved resistance ratio of ~40 as compared to TiOxN device (~7). The switching mechanism is attributed to the formation/dissolution of Oxygen vacancy filament. The memory device has shown good read endurance of >7.5×105 cycles and excellent data retention of >5 hours at 85°C.
    VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on; 01/2013
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    ABSTRACT: Resistive switching properties of a memory device in an IrOx/TaOx/WOx/W structure have been investigated. High-resolution transmission electron microscopy image has shown the formation of a bilayer structure of TaOx/WOx which is further confirmed by energy dispersive X-ray spectroscopy and X-ray photo-electron spectroscopy analyses. The underlying switching mechanism is successfully explained by providing various electrical measurements such as device area dependency on set/reset voltage and low resistance state. A model based on oxygen ions migration is then proposed. Cumulative probability plots of essential memory parameters such as set/reset voltage and LRS/HRS show good distribution. The device has shown excellent read endurance of >105 times and data retention of >104 s with a resistance ratio of >102 at 85 °C.
    Solid-State Electronics 11/2012; 77:35–40. · 1.48 Impact Factor
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    ABSTRACT: This paper investigates the repeatable unipolar/bipolar resistive switching memory characteristics in a copper/germanium-oxide/tungsten (Cu/GeOx/W) structure. The switching mechanism occurs because of the lower barrier height for hole injection rather than electron injection. Therefore, Cu ions, as a positive charge, migrate before initiating growth at the GeOx/W interface and dissolving at the GeOx/Cu interface. The diameter of the Cu nanofilament increases linearly from 0.13 Å to 25 nm as current compliances increase from 1 nA to 10 mA, as calculated using the other approach. The crystalline Cu nanofilament was also confirmed by high-resolution transmission electron microscopy analysis under SET. Good data retention with high resistance ratios of 102–105 (and >104 at 85 °C) and ∼109 was obtained under the bipolar and unipolar modes, respectively. Therefore, a maximum memory size of 5000 Pbit/in2 can be designed in the future.
    Applied Physics Letters 08/2012; 101(7):073106. · 3.79 Impact Factor
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    221st ECS Meeting; 05/2012
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    ABSTRACT: Influence of GeOx layer on resistive switching memory performance in a simple and CMOS compatible W/WOx/GeOx:WOx mixture/W structure has been investigated for the first time. All layers are confirmed by both HRTEM and XPS. This memory device has enhanced performance in terms of the resistance ratio, uniformity, and program/erase cycles as compared to W/WOx/W structure. An excellent read endurance and program/erase cycles of >;10^6 at large Vread of ±1V are obtained. Furthermore, the memory device exhibits robust data retention at 85°C. This device can be operated as low current as 0.1 μA.
    VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on; 04/2012
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    ABSTRACT: The impact of a TaOx nanolayer at the GeSex/W interface on the performance of resistive switching memory in an Al/Cu/GeSex/TaOx/W structure has been examined. All materials and the memory structure have been investigated using high-resolution transmission electron microscopy, energy dispersive x ray spectroscopy, and x ray photo-electron spectroscopy analyses. A conically shaped crystalline Cu (111) nanofilament with a diameter of around 17 nm in the TaOx nanolayer after a current compliance (CC) of 500 μA has been observed, and this has been also characterized by fast Fourier transform. The low resistance state (LRS) decreases as the current compliances (CCs) increased from 1 nA to 1 mA, since the nanofilament diameter increased from 0.04 to 23.4 nm. This is also estimated by bipolar resistive switching characteristics. The resistivity of this crystalline Cu nanofilament is approximately 2300 μΩ.cm. The nanofilament has a cylindrical shape, with CCs ranging from 1 nA to 10 μA and a conical shape with CCs ranging from 50 μA-1 mA. The resistive switching mechanism has been explained successfully under SET and RESET operations. Improved resistive switching parameters, such as SET voltage, LRS, and high resistance state with consecutive switching cycles are obtained and compared to those of pure GeSex and TaOx materials. Extrapolated, long program/erase endurance of > 106 cycles, attributed to the Al/Cu/GeSex/TaOx/W structure design, is observed. This resistive switching memory structure shows extrapolated 10 years data retention with a resistance ratio of > 10 at a low CC of 0.1 μA at 50 °C. A large memory size of ∼ 6 Pbit/sq. in. is obtained, considering the nanofilament diameter at a low CC of 0.1 μA. This study is important not only for improving the performance of low-power resistive switching memory, but also helpful for designing other nonvolatile memory devices.
    Journal of Applied Physics 03/2012; 111(6):063710. · 2.21 Impact Factor
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    ABSTRACT: The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.
    Silicon Nanoelectronics Workshop (SNW), 2012 IEEE; 01/2012
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    ABSTRACT: The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.
    IEDM 2011; 12/2011
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    ABSTRACT: The ambipolar switching diodes with poly-Si n/p/n were successfully demonstrated for cross-point memory applications, such as RRAM. The high JON ~ 0.1 MA/cm2 was obtained to provide memory programming for area = 2.25 x 10-8 cm2. Both negative and positive biases made the positive shift of the J-V curve with DC stress 100 sec and were contributed by acceptor-like defect formation. However, the reliability is sufficient for >;106 cycles of 100 ns operation (~0.1 s total stress at 4V). VBD of 2.25 x 10-8 cm was estimated >; 1V for 10 years. Finally, the authors are very grateful for the support and funding provided by the National Science Council (NSC 98-2221-E-003-020-MY3), for carrying out the process by National Nano Device Laboratories (NDL).
    Device Research Conference (DRC), 2011 69th Annual; 01/2011
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    ABSTRACT: Improved resistive switching memory characteristics in a W/Ti/Ta2O5/W device with a small size of 150 nm have been investigated for the first time. TEM image shows amorphous Ta2O5 film with a thickness of ~7 nm. Memory device has a good repeatable bipolar memory behavior and a large sensing margin of ~2000. The memory device has shown good endurance of at least 104 cycles and excellent data retention at 85°C.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2011;
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    ABSTRACT: Annealing effects on electrical characteristics and reliability of MOS device with HfO2 or Ti/HfO2 high-k dielectric are studied in this work. For the sample with Ti/HfO2 higher-k dielectric after a post-metallization annealing (PMA) at 600°C, its equivalent oxide thickness value is 7.6Å and the leakage density is about 4.5×10−2A/cm2. As the PMA is above 700°C, the electrical characteristics of MOS device would be severely degraded.
    Microelectronic Engineering - MICROELECTRON ENG. 01/2011; 88(7):1309-1311.
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    ABSTRACT: The (anode) TiN/Ti/HfO2/TiN (cathode) resistive random access memory (RRAM) has shown yield ~100%. Its simple metal-insulator-metal (MIM) structure exhibits great potential for an embedded BEOL memory compatible with the high-k/metal gate CMOS process. There have been many theories of RRAM physical mechanism in the literature. This paper focuses on HfO2-based RRAM and describes a complete physical mechanism from forming, SET/RESET, current conduction, to explanations of various observed phenomena including multilevel, cell size scaling, resistance fluctuation, soft error, and non-abrupt RESRT process. Finally, suggestions for device optimization are given based on the physical model.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2011;
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    ABSTRACT: A parameterized SPICE macromodel of resistive random acess memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence. I. INTRODUCTION Nonvolatile memory (NVM) of the resistive switching family has been studied a lot these days as the next-generation memory beyond the mainstream flash memory. One of the most promising candidates is RRAM. Our previous work [1] has demonstrated an HfO2-based bipolar RRAM with high yield and good reliability. Following that, this work presents a parameterized SPICE macromodel to facilitate the RRAM chip design. The SPICE model is based on the data extracted from the HfO2-based RRAM. Fig. 1 shows the sandwich structure of the RRAM with top and bottom TiN electrodes. The Ti layer in the stack serves as an oxygen getter. It will produce more oxygen vacancies in the HfOx layer for better resistive switching phenomenon [1].
    01/2011;
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    ABSTRACT: Phase-change memory (PCM), although promising operative at room temperature, is struggling to achieve ten-year data retention over 100°C. We disclose here that a PCM device made of the composition Ga<sub>25</sub>Te<sub>8</sub>Sb<sub>67</sub> exhibits normal operation at 100°C for an endurance of at least 3 × 10<sup>5</sup> cycles. At room temperature, the endurance is at least 5 × 10<sup>6</sup> cycles. The set-reset speed of the devices reaches 20 ns, and the reset current is around 20% less than that of our reference test cells made of the benchmark Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>.
    IEEE Electron Device Letters 09/2010; · 2.79 Impact Factor

Publication Stats

447 Citations
107.17 Total Impact Points

Institutions

  • 2003–2013
    • Industrial Technology Research Institute
      • Electronics and Optoelectronics Research Laboratories
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2010–2012
    • Kunshan Industrial Technology Research Institute
      Wu-hsien, Jiangsu Sheng, China
    • National Ilan University
      I-lan-hsien, Taiwan, Taiwan
  • 2009
    • National Cheng Kung University
      • Department of Mechanical Engineering
      Tainan, Taiwan, Taiwan
  • 2007–2009
    • Chang Gung University
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2007–2008
    • National Tsing Hua University
      • Department of Engineering and System Science
      Hsinchu, Taiwan, Taiwan
  • 2003–2004
    • National Central University
      • • Department of Electrical Engineering
      • • Department of Physics
      Taoyuan City, Taiwan, Taiwan