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Y. Takai, M. Fujita,
K. Nagata,
S. Isa,
S. Nakazawa,
A. Hirobe,
H. Ohkubo,
M. Sakao,
S. Horiba,
T. Fukase, [......],
N. Nakanishi,
T. Oikawa,
M. Igeta,
H. Tanabe,
H. Miyamoto,
T. Hashimoto,
H. Yamaguchi,
K. Koyama,
Y. Kobayashi,
T. Okuda
[show abstract]
[hide abstract]
ABSTRACT: This paper describes three circuit technologies indispensable for
high-bandwidth multibank DRAM's. (1) A clock generator based on a
bidirectional delay (BDD) eliminates the output skew. The BDD measures
the cycle time as the quantity charged or discharged of an analog
quantity, and replicates it in the next cycle. This achieves a 0.18-mm
<sup>2</sup>, two-cycle-lock clock generator operating from 25 to 167
MHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates the
internal skew caused by the difference between a rise input and a fall
input by 40%. (3) An interbank shared redundancy scheme (ISR) with a
variable unit redundancy (VUR) efficiently increases yield in multibank
DRAM's. The ISR allows redundancy match circuits to be shared with two
or more banks. The VUR allows the number of units replaced to be
variable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank,
1-Gb double-data-rate synchronous DRAM
IEEE Journal of Solid-State Circuits 03/2000; · 3.23 Impact Factor
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Y. Takai, M. Fujita,
K. Nagata,
S. Isa,
S. Nakazawa,
A. Hirobe,
H. Ohkubo,
M. Sakao,
S. Horiba,
T. Fukase, [......],
N. Nakanishi,
T. Olkawa,
M. Igeta,
H. Tanabe,
H. Miyamoto,
T. Hashimoto,
H. Yamaguchi,
K. Koyama,
Y. Kobayashi,
T. Okuda
[show abstract]
[hide abstract]
ABSTRACT: Describes a 1Gb double data rate (DDR) SDRAM which employs: 1) a
clock generator that consists of a bidirectional delay (BDD), 2) a
quadcoupled receiver (QCR), and 3) an inter-bank shared redundancy (ISR)
scheme with a variable unit redundancy (VUR)
Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International; 02/1999
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T. Saeki,
Y. Nakaoka, M. Fujita,
A. Tanaka,
K. Nagata,
K. Sakakibara,
T. Matano,
Y. Hoshino,
K. Miyano,
S. Isa, [......],
K. Yoshino,
S. Hashimoto,
T. Yoshii,
M. Ichinose,
T. Imura,
M. Uziie,
S. Kikuchi,
K. Koyama,
Y. Fukuzo,
T. Okuda
[show abstract]
[hide abstract]
ABSTRACT: A 256-Mb SDRAM (245.7 mm<sup>2</sup>) has been developed using (1)
a high cell occupation ratio (60.2%) array design for chip size
reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using
a first-in first-out (FIFO) buffer with parallel serial converter for
250-MHz clock frequency operation, and (3) a synchronous mirror delay
(SMD) circuit for 2.5-ns clock access and low standby current
IEEE Journal of Solid-State Circuits 12/1996; · 3.23 Impact Factor
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T Saeki,
Y Nakaoka, M Fujita,
A Tanaka,
K Nagata,
K Sakakibara,
T. Matano,
Y Hoshino,
K Miyano,
S. Isa, [......],
K Yoshida,
H Yoshino,
S Hashimoto,
T. Yoshii,
M Ichinose,
T. Imura,
M. Uziie,
K Koyama,
Y. Fukuzo,
T Okuda
[show abstract]
[hide abstract]
ABSTRACT: A 245.7 mm<sup>2</sup> 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International; 03/1996
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T. Sugibayashi,
T. Takeshima,
I. Naritake,
T. Matano,
H. Takada,
Y. Aimoto,
K. Furuta, M. Fujita,
T. Saeki,
H. Sugawara, [......],
N. Kasai,
K. Shibahara,
K. Nakajima,
H. Hada,
T. Hamada,
N. Aizaki,
T. Kunio,
E. Kakehashi,
K. Masumori,
T. Tanigawa
[show abstract]
[hide abstract]
ABSTRACT: A 256-Mb DRAM with a multidivided array structure has been
developed and fabricated with 0.25-μm CMOS technology. It features
30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns
cycle time. Three key circuit technologies were used in its design: a
partial cell array activation scheme for reducing power-line voltage
bounce and operating current, a selective pull-up data-line architecture
to increase I/O width and reduce power dissipation, and a time-sharing
refresh scheme to maintain the conventional refresh period without
reducing operational margin. Memory cell size was 0.72
μm<sup>2</sup>. Use of the trench isolated cell transistor and the
HSG cylindrical stacked capacitor cells helped reduce chip size to 333
mm<sup>2</sup>
IEEE Journal of Solid-State Circuits 12/1993; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on; 06/1993
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T. Sugibayashi,
T Takeshima,
I. Naritake,
T. Matano,
H Takada,
Y. Aimoto,
K Furuta, M Fujita,
T Saeki,
H Sugawara, [......],
N Kasai,
K Shibahara,
K Nakajima,
H. Hada,
T Hamada,
N. Aizaki,
T. Kunio,
E. Kakehashi,
K. Masumori,
T Tanigawa
[show abstract]
[hide abstract]
ABSTRACT: A 256-Mb DRAM (dynamic random-access memory) fabricated using 0.25-μm CMOS technology is described. The DRAM has 16-b I/Os, 30-ns access time, and 35-mA operating current for 60-ns cycle time. Key circuits include a partial cell array activation scheme in a multidivided array structure with a dual word-line format for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O (input/output) width and to reduce current, and a time-sharing refresh to maintain a conventional refresh period without increasing power-line voltage bounce
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International; 03/1993
