ABSTRACT: It is clearly demonstrated that source/drain (S/D) elevation is remarkably effective in suppressing the short channel effect against the shrinkage of gate sidewall spacers in MOSFETs. Even if the gate sidewall width is reduced to as very thin as 15 nm, the short channel effect is effectively suppressed by means of the highly elevated S/D regions (80 nm in the present case), though the characteristics of conventional MOSFETs are drastically degraded. This result is explained in terms of the fact that the serious influence due to the deep S/D implantation is suppressed by the formation of a quasi-single-drain configuration. Furthermore, the parasitic S/D resistance decrease, which will bring about drivability enhancement, was observed for reduction in the sidewall width. These favorable experimental results may indicate the definite necessity of elevated S/D engineering for future ultrashort MOSFETs.
IEEE Electron Device Letters 08/2001; · 2.85 Impact Factor