K. S. Yew

Nanyang Technological University, Tumasik, Singapore

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Publications (7)10.76 Total impact

  • K. S. Yew, D. S. Ang, L. J. Tang
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    ABSTRACT: We show that multistep deposition cum two-step annealing, comprising an ultraviolet ozone (UVO) anneal followed by a low-temperature rapid thermal anneal (RTA), can significantly improve the performance and reliability of a 7.5-angstrom-equivalent-oxide-thickness (EOT) HfO2/TiN gate stack, comprising a 25-angstrom HfO2 on similar to 3 angstrom SiOx, i.e., prepared from direct HfO2 deposition onto an HF-last Si surface. The method yields approximately two orders of magnitude reduction in gate current density and approximately an order of magnitude longer time to breakdown, as compared with the as-deposited gate stack. The observed improvements may be attributed to the "repair" of oxygen-vacancy defects at the HfO2/Si interface and in the HfO2 bulk by the absorbed ozone, through thermal activation provided by the RTA step. The findings provide a promising means for realizing low-leakage and reliable sub-1-nm EOT HfO2/TiN stacks for high-k last integration.
    IEEE Electron Device Letters 02/2013; 34(2):295-297. DOI:10.1109/LED.2012.2231394 · 3.02 Impact Factor
  • K. S. Yew, D. S. Ang
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    ABSTRACT: The TiN/HfZrO/SiOx gate stack formed via multi-step deposition cum room-temperature ultraviolet-ozone (UVO) anneal was examined using scanning tunneling microscopy and pulse capacitance-voltage measurement, and the results were compared with those of the as-deposited (as-dep) and rapid-thermal-annealed (RTA) samples. Evidence shows that a large part of the improvement seen in the multistep-deposited cum UVO-annealed sample, relative to the RTA sample, is a direct consequence of suppressed crystallization of the HfZrO and, hence, a reduction in the density of grain-boundary-related defects. Compared with the as-dep sample, the observed improvement due to UVO annealing is marginal, although further improvement, ascribed to the elimination of oxygen-vacancy defects, may be achieved by either increasing the UVO anneal time after each deposition step or increasing the number of deposition steps. This makes multistep deposition and UVO annealing viable for further enhancing the robustness of the high-k gate dielectric in a gate-last process.
    IEEE Transactions on Electron Devices 08/2012; 59(8):2268-2272. DOI:10.1109/TED.2012.2196702 · 2.36 Impact Factor
  • K. S. Yew, D. S. Ang, G. Bersuker
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    ABSTRACT: We provide new insights, via nanoscale TDDB testing, into the bimodal Weibull failure distribution obtained from area scaling of high-kappa (HK) gate stack. Time-to-breakdown (BD) statistics for grain boundary (GB) and grain in a polycrystalline HK gate stack are obtained individually from localized constant voltage stressing via a scanning tunneling microscope. In spite of an initial difference in the preexisting defect density, no apparent difference in the Weibull slope is observed for the two sets of BD statistics. The bimodal Weibull distribution is shown to be a combined effect: 1) The steep Weibull slope of the lower percentile, arising from large-area devices, is related to BD at GBs, and 2) the upper percentile, arising from small-area devices, is mostly related to grain BDs. In this case, the Weibull slope is reduced by a small fraction of these devices exhibiting early failures due to GB BDs. We show directly that structural defects in an HK dielectric, particularly GBs, play an important role on its BD distribution.
    IEEE Electron Device Letters 02/2012; 33(2):146-148. DOI:10.1109/LED.2011.2174606 · 3.02 Impact Factor
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    ABSTRACT: Electrical and reliability characteristics of the HfSiO x high-permittivity (high-k) gate dielectric formed via a single-step and a multi-step deposition-cum-annealing method are examined via ultrahigh-vacuum scanning tunneling microscopy (STM). Unlike the single-step high-k, which exhibits coarse granular features indicating that transformation to a polycrystalline phase has occurred, the multi-step high-k of equivalent physical thickness is observed to retain the nanocrystalline STM characteristics following a high temperature (∼1000°C) anneal. After the localized electrical stress using the STM probe, the multi-step high-k film shows better leakage current uniformity and higher breakdown voltage comparing to those of the single-step film, consistent with the results of the metal-oxide-semiconductor capacitor measurements. The improvements may be ascribed to a partially suppressed formation of the grain boundaries in thin films constituting the multi-step dielectric, which reduces the grain-boundary related low-resistance paths through the dielectric. The results indicate that the multi-step deposition process can improve electrical characteristics of the high-k gate dielectrics.
    09/2011; 158(10):H1021-H1026. DOI:10.1149/1.3622344
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    ABSTRACT: In this brief, high-κ HfZrO (via atomic layer deposition) fabricated by a novel multideposition multiroom-temperature annealing (MDMA) technique in ultraviolet-ozone (UVO) ambient is systematically investigated by both electrical and physical characterization and is integrated with a TiN metal gate in a gate-last process. Compared with the conventional rapid-thermal-annealed sample, it is found that the device annealed via MDMA in UVO demonstrates the following: 1) more than one order of leakage current reduction at 25°C and 125°C without an equivalent oxide thickness penalty; 2) less susceptibility to stress-induced degradation; and 3) improved time-dependent dielectric-breakdown lifetime. Grain boundary suppression and healing of oxygen vacancies are believed to be responsible for the improvement, as evidenced by scanning tunneling microscopy and X-ray photoelectron spectroscopy analysis.
    IEEE Transactions on Electron Devices 08/2011; DOI:10.1109/TED.2011.2140117 · 2.36 Impact Factor
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    ABSTRACT: A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO<sub>2</sub> layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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    ABSTRACT: ALD HfZrO high-K fabricated by novel multi deposition multi annealing (MDMA) technique at room temperature in Ultraviolet-Ozone (UVO) ambient is systematically investigated for the first time via both physical and electrical characterization. As compared to the reference gate stack treated by conventional rapid thermal annealing (RTA) @ 600°C for 30 s (with PVD TiN electrode), the devices receiving MDMA in UVO demonstrates: 1) more than one order of magnitude leakage reduction without EOT penalty at both room temperature and an elevated temperature of 125°C; 2) much improved stress induced degradation in term of leakage increase and flat band voltage shift (both room temperature and 125°C); 3) enhanced dielectrics break-down strength and time-dependent-dielectric-breakdown (TDDB) life time. The improvement strongly correlates with the cycle number of deposition and annealing (D&A, while keeping the total annealing time and total dielectrics thickness as the same). Scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS) analysis suggest both oxygen vacancies (Vo) and grain boundaries suppression in the MDMA treated samples are likely responsible for the device improvement. The novel room temperature UVO annealing is promising for the gate stack technology in a gate last integration scheme.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010; DOI:10.1109/IEDM.2010.5703343