Publications (1)0 Total impact
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Conference Proceeding: High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects
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ABSTRACT: High-performance 0.13-μm CMOS logic technology has been developed using partially-depleted SOI transistors, EB lithography, and seven-layer copper dual-damascene interconnects with an organic very-low-k dielectric. The technology achieves 9-psec inverter delay at 1.3 V, a 60-mΩ/□ sheet resistance of interconnects, and a 30% smaller intra-layer capacitance than USG. This technology is applied to 1.5-GHz MPU chipsVLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
Institutions
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2000
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Fujitsu Ltd.
Kawasaki, Kanagawa-ken, Japan
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