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M. Hamaguchi,
H. Yin,
K.L. Saenger,
C.Y. Sung,
R. Hasumi,
R. Iijima, K. Ohuchi,
Y. Takasu,
J.A. Ott,
H. Kang, [......],
R. Zhang,
N. Rovedo,
H. Utomo,
K. Fogel,
J.P. de Souza,
D.K. Sadana,
M. Takayanagi,
D. Park,
G. Shahidi,
K. Ishimaru
[show abstract]
[hide abstract]
ABSTRACT: Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (L<sub>g</sub>= 2 mum), 10% higher at short channel (L<sub>g</sub> = 36 nm) compared to (110) bulk PFETs. Moreover, we found that the thinner DSB shows better V<sub>t</sub> roll-off characteristics. On the other hand, NFETs on DSB are as good as (100) bulk NFETs. Thin DSB substrate demonstrates 11% faster ring oscillator speed over thick DSB substrate and 30% faster over (100) bulk due to higher mobility and lower capacitance.
VLSI Technology, 2008 Symposium on; 07/2008
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K. Ohuchi,
C. Lavoie,
C.E. Murray,
C.P. D'Emic,
I. Lauer,
J.O. Chu,
Bin Yang,
P. Besser,
L.M. Gignac,
J. Bruley, [......],
A.W. Topol,
M.J. Rooks,
J.J. Bucchignano,
V. Narayanan,
M. Khare,
M. Takayanagi,
K. Ishimaru,
Dae-Gyu Park,
G. Shahidi,
P.M. Solomon
[show abstract]
[hide abstract]
ABSTRACT: This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10<sup>-8</sup> Omega-cm<sup>2</sup> for both n<sup>+</sup> and p<sup>+</sup> Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.
Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on; 06/2008
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Haizhou Yin,
M. Hamaguchi,
K.L. Saenger,
C.Y. Sung,
R. Hasumi, K Ohuchi,
R Zhang,
J Cai,
J.A. Ott,
X Chen, [......],
N. Rovedo,
K. Fogel,
G. Pfeiffer,
R. Kleinhenz,
D.K. Sadana,
M Takayanagi,
K. Ishimaru,
T.H. Ning,
D.-G. Park,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: End-of-range (EOR) defects generated during the crystal orientation conversion process in DSB technology can give rise to various types of junction leakage depending on their locations relative to device structures. A wide range of EOR defect depths are investigated. Shallow-implant-induced EOR defects (~100 nm) are found to minimize junction leakages due to EOR defects being outside of junction depletion regions. These implant conditions produce no adverse impact on source/drain channel leakage, suggesting that the crystal conversion process is optimized by shallow implants.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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K. Ohuchi,
C. Lavoie,
C. Murray,
C. D'Emic,
J.O. Chu,
Bin Yang,
P. Besser,
L. Gignac,
J. Bruley,
G.U. Singco, [......],
A.W. Topol,
M.J. Rooks,
J.J. Bucchignano,
V. Narayanan,
M. Khare,
M. Takayanagi,
K. Ishimaru,
Dae-Gyu Park,
G. Shahidi,
P. Solomon
[show abstract]
[hide abstract]
ABSTRACT: This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10<sup>-8</sup> Omega-cm<sup>2</sup> for both n<sup>+</sup> and p<sup>+</sup> Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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A. Hokazono,
S. Kawanaka,
K. Tsumura,
Y. Hayashi,
H. Tanimoto,
T. Enda,
N. Aoki, K. Ohuchi,
S. Inaba,
K. Okano,
M. Fujiwara,
T. Morooka,
M. Goto,
A. Kajita,
T. Usui,
K. Ishimaru,
Y. Toyoshima
[show abstract]
[hide abstract]
ABSTRACT: Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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Applied Physics Letters. 01/2007; 90(19):192103.
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N. Yasutake,
T. Ishida, K. Ohuchi,
N. Aoki,
N. Kusunoki,
S. Mori,
I. Mizushima,
T. Morooka,
K. Yahashi,
S. Kawanaka,
K. Ishimaru,
H. Tshiuchi
[show abstract]
[hide abstract]
ABSTRACT: A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451muA/mum at verbar;V<sub>dd</sub>| of 0.9V, I<sub>off</sub> of 100 nA/mum (552 muA/mum at |V<sub>dd</sub> | of 1.0V). Furthermore, by combining with V<sub>dd</sub> scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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M. Fujiwara,
T. Morooka,
N. Yasutake, K. Ohuchi,
N. Aoki,
H. Tanimoto,
M. Kondo,
K. Miyano,
S. Inaba,
K. Ishimaru,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T<sub>BOX</sub> is varied from 5 nm to 145 nm. In addition, optimum design regions of T<sub>BOX</sub> for achieving performance requirements are demonstrated.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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K. Adachi, K. Ohuchi,
N. Aoki,
H. Tsujii,
T. Ito,
H. Itokawa,
K. Matsuo,
K. Suguro,
Y. Honguh,
N. Tamaoki,
K. Ishimaru,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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[show abstract]
[hide abstract]
ABSTRACT: We fabricated MOSFET devices using flash lamp annealing (FLA), and studied the halo profile dependence on CMOSFETs performance. Although FLA is high temperature anneal of 1000°C or more and has soaking time corresponding to millisecond, it causes anomalous low level of halo dopant activation and redistribution. This anomaly degrades threshold voltage roll-off characteristics and Ion-Ioff characteristics. In this paper, we investigated halo dopant redistribution at each process step and the halo condition dependence of CMOSFETs characteristics, and proposed the design guideline of halo condition using FLA.
Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on; 07/2005
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H. Kawasaki, K. Ohuchi,
A. Oishi,
O. Fujii,
H. Tsujii,
T. Ishida,
K. Kasai,
Y. Okayama,
K. Kojima,
K. Adachi,
N. Aoki,
T. Kanemura,
D. Hagishima,
M. Fujiwara,
S. Inaba,
K. Ishimaru,
N. Nagashima,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: This paper discusses the root causes of the fact that only slight performance improvement of MOSFET with strained-Si substrate has been achieved in short channel region (L < 100 nm). The performance improvement in short channel region is found to deteriorate mainly due to the parasitic resistance increase and tensile stress relaxation in the strained-Si layer. In regard to the parasitic resistance and the stress relaxation in small device geometry, the scaling impacts of strained-Si layer thickness (T<sub>ss</sub>) are investigated from the viewpoint of both DC and AC characteristics. Within this work, T<sub>ss</sub> reduction down to 5 nm improves the current drive (I<sub>d</sub>) of nFET up to 6 % (L < 50 nm) compared with conventional bulk nFET. Propagation delay time (τ<sub>pd</sub>) improvement in CMOS inverter is also observed to be more than 15 %. Finally, the impurity profile optimization is proposed to improve MOSFET performance toward the 45 nm node CMOS era.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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S. Inaba,
K. Miyano,
H. Nagano,
A. Hokazono, K. Ohuchi,
I. Mizushima,
H. Oyamatsu,
Y. Tsunashima,
K. Ishimaru,
Y. Toyoshima,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C<sub>j</sub>) has been reduced in SODEL FET, i.e., C<sub>j</sub> (area) was ∼0.73 fF/μm<sup>2</sup> both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient γ is also reduced to less than 0.02 V<sup>1</sup>2/. Nevertheless, current drives of 886 μA/μm (I<sub>off</sub>=15 nA/μm) in nFET and -320 μA/μm (I<sub>off</sub>=10 nA/μm) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V<sub>dd</sub>|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.
IEEE Transactions on Electron Devices 10/2004; · 2.32 Impact Factor
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N. Yasutake, K. Ohuchi,
M. Fujiwara,
K. Adachi,
A. Hokazono,
K. Kojima,
N. Aoki,
H. Suto,
T. Watanabe,
T. Morooka, [......],
M. Ohmura,
K. Miyano,
H. Yamada,
H. Tomita,
D. Matsushita,
K. Muraoka,
S. Inaba,
M. Takayanagi,
K. Ishimaru,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V<sub>dd</sub> condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f<sub>i</sub> is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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[show abstract]
[hide abstract]
ABSTRACT: Nickel monosilicide (NiSi) is considered to be a promising candidate for the self-aligned silicide (SALICIDE) material of 65 nm node MOSFETs and beyond. Therefore, an accurate simulation method for the NiSi SALICIDE process is required in order to design the optimum device. We realize, for the first time, the integrated simulation with silicide topography and Schottky contact models, and propose a calibration strategy of contact resistance. In this paper, we demonstrate the accurate simulation results of the silicide both in terms of its topography and contact resistance for the NiSi SALICIDE process.
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
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[show abstract]
[hide abstract]
ABSTRACT: Source/drain extension engineering using a offset spacer for the 65 nm node high performance CMOS was investigated. Although a current drivability was degraded with increasing the offset spacer width, the improvement in the tolerance of short channel effect and the reduction of the overlap capacitance between the gate electrode and the source/drain extension were achieved. There exists an optimum spacer width from the AC performance viewpoint.
Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on; 01/2003
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[show abstract]
[hide abstract]
ABSTRACT: Silicide technology for ultra-shallow junction in next technology node is discussed. Salicide material is changed from low resistivity refractory metal silicide to near-noble metal silicide from the view point of less consumption of Si by silicidation. The pn junction leakage for shallow S/D can be drastically improved by NiSi as compared with CoSi<sub>2</sub>.
Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on; 01/2003
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S. Inaba,
K. Okano,
S. Matsuda,
M. Fujiwara,
A. Hokazono,
K. Adachi, K. Ohuchi,
H. Suto,
H. Fukui,
T. Shimizu, [......],
T. Kudo,
H. Shibata,
S. Taniguchi,
M. Takayanagi,
A. Azuma,
H. Oyamatsu,
K. Suguro,
Y. Katsumata,
Y. Toyoshima,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I<sub>g</sub> and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 μA/μm in nFET and 272 μA/μm in pFET at V<sub>dd</sub>=0.85 V (at I<sub>off</sub>=100 nA/μm) were achieved and they are the best values for 35 nm gate length CMOS reported to date.
IEEE Transactions on Electron Devices 01/2003; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: ITRS2001 indicates 25-nm physical gate length and 10-17-nm extension depth are required in 65-nm technology node for high performance application. It means resultant requirement of precisely controlled conventional process and new material and process introduction. Though ion implantation and spike RTA are still base line technology for doping, it should be carefully optimized in process integration avoiding implantation-induced damage and transient enhanced diffusion. Careless process sequence might cause undesired enlargement of junction depth even in LPCVD temperature annealing. Sidewall scaling is also necessary to reduce source and drain parasitic resistance and it relates to the contact junctions and silicidation process. Cobalt salicide is widely used in recent technology node. However, its silicon consumption in silicidation process requires relatively deep contact junctions and tends to cause the interference of the contact junction to the channel region. Therefore, lower silicon consumption silicide material such as nickel SALICIDE is one of the solutions. NiSi silicidation can be performed at low temperature and silicon consumption is about 80% of CoSi2 silicide under the same silicide thickness condition. Additionally, more structural approach like elevated source/drain using selective silicon or silicon-germanium will be introduced to solve severer constraints.
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on; 10/2002
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N. Yanagiya,
S. Matsuda,
S. Inaba,
M. Takayanagi,
I. Mizushima, K. Ohuchi,
K. Okano,
K. Takahasi,
E. Morifuji,
M. Kanda, [......],
M. Moriuchi,
M. Kishida,
H. Matsumori,
H. Harakawa,
H. Oyamatsu,
N. Nagashima,
S. Yamada,
T. Noguchi,
H. Okamoto,
M. Kakumu
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFET's in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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A. Hokazono, K. Ohuchi,
M. Takayanagi,
Y. Watanabe,
S. Magoshi,
Y. Kato,
T. Shimizu,
S. Mori,
H. Oguma,
T. Sasaki,
H. Yoshimura,
K. Miyano,
N. Yasutake,
H. Suto,
K. Adachi,
H. Fukui,
T. Watanabe,
N. Tamaoki,
Y. Toyoshima,
H. Ishiuchi
[show abstract]
[hide abstract]
ABSTRACT: High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
