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D.A. Rich,
M.S. Carroll, M.R. Frei,
T.G. Ivanov,
M. Mastrapasqua,
S. Moinian,
A.S. Chen,
C.A. King,
E. Harris,
J. De Blauwe,
Hong-Ha Vuong,
V. Archer,
K. Ng
[show abstract]
[hide abstract]
ABSTRACT: As process technology advances, we will see SoC systems with
millions of digital gates combined with RF circuits operating in the
tens of GHz
IEEE Microwave Magazine 07/2002; · 2.11 Impact Factor
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M. Mastrapasqua,
P. Palestri,
A. Pacelli,
G.K. Celler, M.R. Frei,
P.R. Smith,
R.W. Johnson,
L. Bizzarro,
W. Lin,
T.G. Ivanov,
M.S. Carroll,
I.C. Kizilyalli,
C.A. King
[show abstract]
[hide abstract]
ABSTRACT: We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.
IEEE Electron Device Letters 04/2002; · 2.85 Impact Factor
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[show abstract]
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ABSTRACT: DC characteristics of a depletion-mode (D-mode) GaAs MOSFET with a thin Ga<sub>2</sub>O<sub>3</sub>(Gd<sub>2</sub>O<sub>3</sub>) gate dielectric layer (74 Å) show low gate leakage current, negligible drain current hysteresis and higher than 10 V gale-drain two-terminal breakdown voltage. Compared to MESFET with the same gate length, channel material and fabricated by the same process, the GaAs MOSFET shows higher unity current gain cutoff frequency (Ft). The higher Ft for the MOSFET than that of the MESFET agrees with earlier theoretical predictions.
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2002. 24th Annual Technical Digest; 02/2002
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[show abstract]
[hide abstract]
ABSTRACT: Employing Ga<sub>2</sub>O<sub>3</sub>(Gd<sub>2</sub>O<sub>3</sub>) as gate dielectric on GaAs, prepared in a multi-chamber MBE system, has resulted in a low interfacial density of states (D<sub>it</sub>). The gate oxide is subjected to photoresists, solvents, water, and air before metallization, and as a consequence, contamination of the gate oxide is inevitable. The authors have studied the effects of gate oxide cleaning and etching before metallization on the DC and RF characteristics of depletion-mode GaAs MOSFETs with Ga<sub>2</sub>O<sub>3</sub>(Gd<sub>2</sub>O<sub>3</sub>) as gate dielectric.
Molecular Beam Epitaxy, 2002 International Conference on; 02/2002
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[show abstract]
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ABSTRACT: We report experimental results demonstrating the use of transient
enhanced diffusion (TED) caused by silicon implant for
“tuning” boron out-diffusion. The effect was measured as a
function of the silicon implant dose and anneal temperature, and a range
of boron junction depth movement from almost none up to 81 nm was
observed with increasing TED at 750°C. The diffused profiles could
be approximated by using a modified solubility limit model to describe
the enhanced boron diffusion and clustering. However, by using a more
sophisticated continuum model based on atomistic calculations, excellent
agreement with the measured profiles could he obtained. In addition, the
fit to the measured data yields the fraction of boron present in
BI<sub>2</sub> precursor clusters after silicon implant as a function of
the silicon implant dose. Two possible applications of the TED
“tuning” are discussed, with device simulations which show
that the effect is sufficiently large to tune the base width of a
bipolar device from being depleted to that suitable for a high
performance device
IEEE Transactions on Electron Devices 08/2000; · 2.32 Impact Factor
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C.A. King, M.R. Frei,
M. Mastrapasqua,
K.K. Ng,
Y.O. Kim,
R.W. Johnson,
S. Moinian,
S. Martin,
H.-I. Cong,
F.P. Klemens, [......],
T.-I. Hsu,
T. Campbell,
S.J. Molloy,
L.B. Fritzinger,
T.G. Ivanov,
K.K. Bourdelle,
C. Lee,
Y.-F. Chyan,
M.S. Carroll,
C.W. Leung
[show abstract]
[hide abstract]
ABSTRACT: We report a new super self-aligned graded SiGe base transistor
that uses high energy implantation, rather than epitaxial growth, to
form the sub-collector region. This new inexpensive process yields a
device with f<sub>T</sub> of 52 GHz and f<sub>max</sub> of 70 GHz with
the addition of only 4 lithography levels over our 0.25 μm CMOS
technology without any changes to the existing process steps. Also, we
demonstrate 4:1 multiplexer and 1:4 demultiplexer circuits using this
technology that show excellent performance at 10 Gbit/s
Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
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M.R. Frei,
N.R. Belk,
D.C. Dennis,
M.S. Carroll,
W. Lin,
M.R. Pinto,
V.D. Archer,
T.G. Ivanov,
S. Moinian,
K.K. Ng,
J. Chu
[show abstract]
[hide abstract]
ABSTRACT: Inductors fabricated using CMOS technologies based on epi/p<sup>+
</sup> substrates are severely degraded because of eddy current losses
in the substrate. We propose and demonstrate a modified substrate
structure, which addresses the conflicting goals of high inductor
quality-factor and high latch-up immunity. Results include fabricated
inductors with Q-factor as high as 16
Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
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01/1999
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Yih-Feng Chyan,
M.S. Carroll,
T.G. Ivanov,
A.S. Chen,
W.J. Nagy,
S. Chaudhry,
R.W. Dail,
V.D. Archer,
K.K. Ng,
S. Martin,
Minseok Oh, M.R. Frei,
I.C. Kizilyalli,
R.Y. Huang,
M.J. Thoma,
C.A. King,
W.T. Cochran,
K.H. Lee
[show abstract]
[hide abstract]
ABSTRACT: A 0.25-μm modular high-energy implanted complementary BiCMOS
(HEICBiC) technology has been developed for wireless-communication
VLSIs. The technology demonstrates a high f<sub>T</sub>=52 GHz and a
high f<sub>T</sub>BV<sub>CEO</sub>=160 GHz-V for single-poly emitter NPN
transistors and a high f<sub>T</sub>=10.7 GHz for implanted-emitter PNP
transistors. It is one of the best results for single-poly
BiCMOS/bipolar technologies without an epitaxial buried collector. In
comparison with 0.25-μm NMOS, HEICBiC shows lower power consumption
and higher RF performance
Bipolar/BiCMOS Circuits and Technology Meeting, 1998. Proceedings of the 1998; 10/1998
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[show abstract]
[hide abstract]
ABSTRACT: Porous Si layers up to 250 μm in thickness are used to isolate
spiral inductors from low resistivity substrates. Wafer curvature and
secondary ion mass spectroscopy (SIMS) analysis are done to address the
manufacturability issue of porous Si. Spiral inductors with a single
level Al on 2 in, p-type substrates of 0.008 Ω-cm resistivity are
demonstrated with Q<6 at 3 GHz for an L of ~8 nH. Large inductors
with L~100 nH have been shown with the first resonance frequency at 1
GHz. The expected performance potential as well as factors that could be
limiting the Q are discussed
IEEE Journal of Solid-State Circuits 10/1998; · 3.23 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: The Johnson limit predicts that due to fundamental material
limitations, the f<sub>t</sub>BV<sub>ceo</sub> product for Si bipolar
transistors cannot exceed 200 GHz-V. Since this limit ignores many
practical components, it should not be achievable experimentally. In
light of the fact that results reaching this limit have been reported,
we have reevaluated such fundamental limits, and have found that this
number should be much higher
IEEE Transactions on Electron Devices 09/1998; · 2.32 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Porous Si layers up to 250 μm in thickness are used to isolate spiral inductors from low resistivity substrates. Wafer curvature and SIMS analysis are done to address the manufacturability issue of porous Si. Spiral inductors with a single level Al on 2-inch, p-type substrates of 0.008 Ω-cm resistivity are demonstrated with Q=5.0 at 1.8 GHz for an L of 9 nH. Large inductors with L~150 nH have been shown with the first resonance frequency at 1 GHz. The expected performance potential as well as factors that could be limiting the Q are discussed
Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the; 10/1997
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[show abstract]
[hide abstract]
ABSTRACT: We report a new Si/SiGe HBT device structure using selective and
non-selective rapid thermal epitaxy. The structure has the potential to
simultaneously provide for high level integration and a high Ge fraction
strained alloy base which allows high base doping. We used an in-situ As
doped polysilicon emitter contact to provide low R<sub>E</sub> (9 to 12
Ω for A<sub>E</sub>=0.5×10 μm<sup>2</sup>) without the
enhanced diffusion effects associated with direct implantation or
phosphorous doped poly emitters. In addition, we studied the effects of
the extrinsic base implant position on the device I-V characteristics,
junction capacitances, and high frequency performance. The collector
current increased by over 3 decades as the extrinsic base implant
position moved from the single crystal region to an adjacent poly region
due to the containment of damage. S-parameter measurements of a
0.5×10 μm<sup>2</sup> device yielded a cutoff frequency of 54
GHz for V<sub>CE</sub>=1.5 V and I<sub>C</sub>=14.8 mA
Electron Devices Meeting, 1995., International; 01/1996
