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ABSTRACT: In this paper, the static and dynamic switching characteristics of Ti/HfO<sub>2</sub>/TiN resistive random access memory (RRAM) have been examined. Based on the experimental results, several pertinent device characteristics can be developed, which include a tunneling barrier width model to explain the RRAM switching behaviors, and the ac transient switching characteristics for circuit model development. We also investigated the potential applications of RRAM as a memristor for both digital and analog circuit design, and discuss the feasibilities and problems to be solved.
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on; 12/2010
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ABSTRACT: In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I<sub>D</sub>-RTN (drain current random telegraph noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
VLSI Technology, 2009 Symposium on; 07/2009
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S.S. Chung,
E.R. Hsieh,
P.W. Liu,
W.T. Chiang,
S.H. Tsai,
T.L. Tsai,
R.M. Huang,
C.H. Tsai,
W.Y. Teng,
C.I. Li,
T.F. Kuo,
Y.R. Wang,
C.L. Yang,
C.T. Tsai,
G.H. Ma,
S.C. Chien,
S.W. Sun
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ABSTRACT: A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I<sub>D,sat</sub> current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%=1.1%), using the poly-gate 40 nm-node Si:C/eSiGe S/D CMOS technology. Moreover, PBTI effect was first observed in this device as a result of carbon impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
VLSI Technology, 2009 Symposium on; 07/2009
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S.S. Chung,
E.R. Hsieh,
D.C. Huang,
C.S. Lai,
C.H. Tsai,
P.W. Liu,
Y.H. Lin,
C.T. Tsai,
G.H. Ma,
S.C. Chien,
S.W. Sun
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ABSTRACT: In this paper, the design guideline with emphasis on CMOS device reliability has been addressed. Advanced 65 nm CMOS devices with various strain engineering were evaluated. For nMOSFETs, charge pumping (CP) measurement is efficient for their reliability characterizations. Although biaxial strained SiGe-channel device provides good driving current enhancement, it suffers from the Ge out-diffusion such that exhibits worse reliability. The SSOI device exhibits good hot-carrier immunity, but its interface quality needs special care during the process. In addition, SiC on S/D device is an alternative for high current enhancement, but its off-state junction leakage is serious. Then, CESL device becomes the most promising technology with high performance and the best reliability, especially with process simplicity. For pMOSFETs, both uniaxial and biaxial strained devices have been studied. For the first time, an accurate representation of interface trap (N<sub>it</sub>) profiling, suitable for HC and NBTI analyses, has been developed by an improved DCIV method. The uniaxial-strained device shows much better reliability, in particular a special class of SiGe S/D device with EDB design seems to be promising. These results provide a valuable guideline for the aggressive design of strained CMOS technologies.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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ABSTRACT: A new method, called gate current random telegraph noise (I<sub>G</sub> RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I<sub>G</sub> RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the soft-breakdown (SBD) behavior of a device can be clearly identified. Its I<sub>G</sub> RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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ABSTRACT: In this paper, the device performance in terms of its transport characteristics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on nMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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ABSTRACT: As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the I<sub>ON</sub> current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications on very high mobility n- and p-MOSFET channel/substrate orientations with various strains have been made. For nMOSFETs, it shows that uniaxial tensile-stress using CESL is more efficient in current enhancement than the biaxial stress with bulk strained-SiGe technique. For the pMOSFETs, compressive stress using uniaxial or biaxial has been evaluated for various structures. It was found that both ballistic efficiency and the injection velocity can be enhanced in a specific pMOS structure with appropriate combination of CESL and biaxial strain. The technology roadmaps have then been established from advanced 65 nm CMOS devices. These results provide a guideline for designing high performance strained technology for CMOS devices in the sub-100 nm regime.
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008
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ABSTRACT: A novel cell operation scheme featuring low voltage, high speed, and excellent data retention has been proposed for SONOS flash memory. First, in 1 bit/cell operation, program is achieved by a back-bias assisted hot hole injection, while erase is achieved by forward-bias assisted electron injection. For a thick tunnel oxide (50 Adeg), the ultra-low voltage (~5 V) and ultra-fast speed (<1musec) operation has been the record reported to date. On the other hand, a 2 bit/cell operation is also demonstrated, in which very good retention can be achieved in comparison to conventional operation schemes, e.g., CHE (channel hot electron) or BTB(Band-to-band) tunneling etc.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: The channel backscattering and injection velocity of carriers in advanced CMOS devices are the two key parameters for achieving high drain current enhancement. For the first time, an extensive study of these transport parameters for different substrate orientations has been evaluated for both nMOSFET and pMOSFET. By suitably choosing the substrate orientation, it may achieve a reduced backscattering and an increased injection velocity, which is preferable for designing high performance logic CMOS devices. Results show that, in pMOSFET, (110) substrate is preferred and current enhancement can be greatly enhanced in the <112> channel. In comparison, (110) substrate in nMOSFET has an adverse effect in reducing driving current as a result of poorer transport characteristics. Therefore, (100) substrate is expected for nMOSFET design. A guideline is then summarized for the optimum design of high performance CMOS devices.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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ABSTRACT: Reliability of ALD (atomic layer deposition) HfSiON high K gate stacks is greatly enhanced with a properly engineered IL (interfacial layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
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ABSTRACT: Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data patterns, typically "All `0'/`1'" and checkerboard. Three error propagation categories with 41 modes inherent in device architectures are identified. Novel MCU features, in which errors can be corrected by rewriting but I<sub>dd</sub> increases stepwise depending on MCU multiplicity, are identified. With "All `0'/`1'" pattern, ratio of double bit error is found to be even higher than that of single bit errors. The majority of the double bit error is in nearest neighborhood (NN) position along word line (WL). Underlining basic mechanism can be either charge collection-diffusion or parasitic bipolar actions. But most features can be elucidated only fully by a novel MCU mechanism MCBI (multi-coupled bipolar interaction) proposed by the authors, giving clues for SEU tolerant sub-100nm design
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
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ABSTRACT: For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I<sub>D</sub> degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V<sub>T</sub> is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I<sub>D</sub> degradation. In addition, the V<sub>T</sub> rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N<sub>2</sub> content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.
IEEE Transactions on Device and Materials Reliability 04/2006; · 1.54 Impact Factor
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S.S. Chung,
Y.R. Liu,
S.J. Wu,
C.S. Lai,
Y.C. Liu,
D.F. Chen,
H.S. Lin,
W.T. Shiau,
C.T. Tsai,
S.C. Chien,
S.W. Sun
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ABSTRACT: In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC (hot carrier) and NBT (negative bias temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (110)/(100) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/( 100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge outdiffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International; 02/2005
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S.S. Chung,
H.J. Feng,
Y.S. Hsich,
A. Liu,
W.M. Lin,
D.F. Chen,
J.H. Ho,
K.T. Huang,
C.L. Yang,
O. Cheng,
Y.C. Sheng,
D.Y. Wu,
W.T. Shiau,
S.C. Chien,
Kuan Liao,
S.W. Sun
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ABSTRACT: A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12A-16A range gate oxide CMOS device has been demonstrated. The approach being taken includes an incremental frequency charge-pumping (IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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ABSTRACT: In this paper, the ONO layer scaling effect and the leakage components in a SONOS cell have been extensively studied. The reliability with focus on both endurance and data retention has been demonstrated. Results show that thinner blocking oxide has better endurance, while it has poorer data retention. For the data retention before cycling, thermionic and direct tunneling, in relation to the data loss, are the two dominant leakage components, which can be separated. Moreover, after cycling, we have been able to separate a third component - the trap-to-trap tunneling current. These results are useful toward an understanding of the leakage mechanisms of SONOS cell as well as the scaling effect of ONO layers.
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the; 08/2004
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ABSTRACT: In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFETs, for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I<sub>D</sub> degradation is due to the channel length shortening, and the electron trap is dominant for the device degradation. While for thin gate oxide, the I<sub>D</sub> degradation is due to width narrowing, and the hole trap is dominant, in which both electron and hole trap induced V<sub>T</sub> shifts are significant. The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV<sub>T</sub> in thin-oxide with reduced width.
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the; 08/2004
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ABSTRACT: In this paper, we will demonstrate two different strategies for designing p-channel flash memories, for achieving better reliability, in particular data retention and drain-disturb. The first one is by using a gate-engineering approach and the other one is using a newly developed substrate bias enhanced Avalanche Hot Electron (AHE) injection programming scheme. For the former, a p-doped floating gate on both p-channel flash cells can be achieved with superior data retention characteristics as well as a 3-order improvement of the drain disturb. For the latter, it exhibits much higher speed and much lower voltage for programming, and very good drain disturb characteristics.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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S.S. Chung
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ABSTRACT: This paper will give an overview of more advanced charge pumping and Gated-Diode techniques for the process and reliability characterization of advanced CMOS devices. Its potential use for the device hot carrier reliability study and process characterization, e.g., oxide quality monitor, plasma-induced oxide damage, and STI effects will be presented. More recent developments for 1nm range ultra-thin gate oxide CMOS device applications will also be demonstrated. Further development and the road-blocks of these techniques will be addressed.
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
