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L.G. Gosset,
V. Arnal,
C. Prindle,
R. Hoofman,
G. Verheijden,
R. Daamen,
L. Broussous,
F. Fusalba,
M. Assous,
R. Chatterjee,
J. Torres,
D. Gravesteijn, K.C. Yu
[show abstract]
[hide abstract]
ABSTRACT: The present paper deals with the different techniques investigated in the whole microelectronics community to integrate air cavities, usually known as air gaps, in-between copper lines for advanced interconnects. The different integration processes were split into two categories, i.e. (i) using a non-conformal CVD deposition inside patterned trenches and (ii) by removing a sacrificial material using a specific technological operation. Advantages and drawbacks of the different approaches will be discussed, including integration issues, manufacturability, and electrical performances. The aim of the paper is to sensitize the BEOL community on these specific approaches that now appear attractive considering the electrical performances required for 45 nm and below technological nodes.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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K.C. Yu,
J. Werking,
C. Prindle,
M. Kiene,
M.-F. Ng,
B. Wilson,
A. Singhal,
T. Stephens,
F. Huang,
T. Sparks, [......],
V. Wang,
T. Lii,
C. King,
P. Crabtree,
J. Farkas,
J. Iacoponi,
J. Pellerin,
B. Melnick,
M. Woo,
E. Weitzman
[show abstract]
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ABSTRACT: The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 μm CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; 02/2002
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A.H. Perera,
B. Smith,
N. Cave,
M. Sureddin,
S. Chheda,
R. Islam,
J. Chang,
S.-C. Song,
A. Sultan,
S. Crown, [......],
T. Lii,
T. Sparks,
T. Stephens,
M. Schaller,
C. Goldberg,
K. Junker,
D. Wristers,
J. Alvis,
B. Melnick,
S. Venkatesan
[show abstract]
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ABSTRACT: A modular 0.13 μm CMOS platform has been developed to support a
wide range of applications, including embedded non-volatile memory
(NVM). The high performance core device with a 18 Å gate oxide
supports the high end needs of the technology. In addition, medium
performance and low leakage 25 Å devices are provided in the
technology platform to service the low power applications, with low
off-state leakage. The peripheral I/O devices support both 2.5 V (50
Å) and 3.3 V (70 Å) interfaces. Gate lengths range from 110
to 80 nm. Optical enhancement techniques allow use of 248 nm KrF
lithography to meet the patterning needs. The interconnect technology
allows for two low-k dielectric options with K-values in the range from
2.9 to 3.6. Aggressive design rules, fully compatible with 248 nm KrF
systems allow for high logic densities and a 2.48 um<sup>2</sup> 6T
embedded SRAM cell. The technology has been exercised using a 4MB SRAM
test vehicle with good yields
Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000
