[Show abstract][Hide abstract] ABSTRACT: This paper proposes an algorithm to minimize the number of edges in an edge-valued multi-valued decision diagram (EVMDD) for fast analysis of multi-state systems. We minimize the number of edges by grouping multi-valued variables into larger-valued variables. By grouping multi-valued variables, we can also reduce the number of nodes. However, minimization of the number of nodes by grouping variables is not always effective for fast analysis of multi-state systems. On the other hand, minimization of the number of edges is effective. Experimental results show that the proposed algorithm for minimizing the number of edges reduces the number of edges by up to 15% and the number of nodes by up to 47%. This results in a speed-up of the analysis of multi-state systems by about three times.
Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on; 01/2013
[Show abstract][Hide abstract] ABSTRACT: We demonstrate a circuit that generates a permutation in response to an index. Since there are n! n-element permutations, the index ranges from 0 to n! - 1. Such a circuit is needed in the hardware implementation of unique-permutation hash functions to specify how parallel machines interact through a shared memory. Such a circuit is also needed in cryptographic applications. The circuit is based on the factorial number system. Here, each non-negative integer is uniquely represented as sn-1(n - 1)! + sn-2(n - 2)! +. . . + s11!, where 1 ≤ si ≤ i. That is, the permutation is produced by generating the digits si in the factorial number system representation of the index. The circuit is combinational and is easily pipelined to produce one permutation per clock period. We give experimental results that show the efficiency of our designs. For example. we show that the rate of production of permutations on the SRC-6 reconfigurable computer is 1,820 times faster than a program on a conventional microprocessor in the case of 10-element permutations. We also show an efficient reconfigurable computer implementation that produces random permutations using the Knuth shuffle algorithm. This is useful in Monte Carlo simulations. For both circuits, the complexity is O(n2), and the delay is O(n).
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International; 01/2012
[Show abstract][Hide abstract] ABSTRACT: This paper proposes new architectures for numeric function generators (NFGs) using piecewise arithmetic expressions. The proposed architectures are programmable, and they realize a wide range of numeric functions. To design an NFG for a given function, we partition the domain of the function into uniform segments, and transform a sub-function in each segment into an arithmetic spectrum. From this arithmetic spectrum, we derive an arithmetic expression, and realize the arithmetic expression with hardware. Since the arithmetic spectrum has many zero coefficients and repeated coefficients, by storing only distinct nonzero coefficients in a table, we can significantly reduce the table size needed to store arithmetic coefficients. Experimental results show that the table size can be reduced to only a small percent of the table size needed to store all the arithmetic coefficients. We also propose techniques to reduce table size further and to improve performance.
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on; 06/2011
[Show abstract][Hide abstract] ABSTRACT: We show the architecture and design of a numeric function generator that realizes, at high speed, arithmetic functions, like log x, sin x, 1 x , etc.. This approach is general; different circuits are not needed for different functions. Further, composite functions, like log (sin ( 1 x )) can be realized as easily as individual functions. A tutorial description of the method is presented, followed by descriptions of the design considerations that must be made. For example, we discuss how circuit complexity increases as the desired approximation error decreases. Also, we discuss enhancements of the basic numeric function generator approach, including higher order polynomial approximations, floating point, and multi-variable implementations.
[Show abstract][Hide abstract] ABSTRACT: This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA)
[Show abstract][Hide abstract] ABSTRACT: The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special significance when BDDs are used in simulation and design verification. A main result of this paper is that the APL for benchmark functions is typically much smaller than for random functions. That is, for the set of all functions, we show that the average APL is close to the maximum path length, whereas benchmark functions show a remarkably small APL. Surprisingly, however, typical functions do not achieve the absolute maximum APL. We show that the parity functions are unique in having that distinction. We show that the APL of a BDD can vary considerably with variable ordering. We derive the APL for various functions, including the AND, OR, threshold, Achilles' heel, and certain arithmetic functions. We show that the unate cascade functions uniquely achieve the absolute minimum APL.
[Show abstract][Hide abstract] ABSTRACT: The availability of large, inexpensive memory has made it possible to realize numerical functions, such as the reciprocal, square root, and trigonometric functions, using a lookup table. This is much faster than by software. However, a naive look-up method requires unreasonably large memory. In this paper, we show the use of a look-up table (LUT) cascade to realize a piecewise linear approximation to the given function. Our approach yields memory of reasonable size and significant accuracy.
[Show abstract][Hide abstract] ABSTRACT: This paper focuses on the average path length (APL) of BDD's for switching functions. APL is a metric for the time it takes to evaluate the function by a computer program. We derive the APL for the AND, OR, parity, carry-out, com-parison, threshold symmetric, and majority functions. We also consider the average of the APL for various classes of functions, including symmetric, threshold symmetric, and unate cascade. For symmetric functions, we show the average APL is close to the maximum path length, n, the number of variables. We show there are exactly two functions, the parity functions, that achieve the upper bound, n, on the APL for BDD's over all functions dependent on n variables. All other functions have an APL strictly less than n. We show that the APL of BDD's over all functions dependent on n variables is bounded below by 2 − 1 2 n−1 . The set of functions that achieves this small value is uniquely the set of unate cascade realizable functions. We also show that the APL for benchmark functions is typically much less than for random functions.
[Show abstract][Hide abstract] ABSTRACT: A function f is AND bi-decomposable if it can be written as f(X
<sub>1</sub>,X<sub>2</sub>)=h<sub>1</sub>(X<sub>1</sub>)h<sub>2</sub>(X
<sub>2</sub>). In this case, a sum-of-products expression (SOP) for f is
obtained from minimum SOPs (MSOP) for h<sub>1</sub> and h<sub>2</sub> by
applying the law of distributivity. If the result is an MSOP, then the
complexity of minimization is reduced. However, the application of the
law of distributivity to MSOPs for h<sub>1</sub> and h<sub>2</sub> does
not always produce an MSOP for f. We show an incompletely specified
function of n(n-1) variables that requires at most n products in an
MSOP, while 2<sup>n-1</sup> products are required by minimizing the
component functions separately. We introduce a new class of logic
functions, called orthodox functions, where the application of the law
of distributivity to MSOPs for component functions of f always produces
an MSOP for f. We show that orthodox functions include all functions
with three of fewer variables, all symmetric functions, all unate
functions, many benchmark functions, and few random functions with many
variables
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific; 02/2001
[Show abstract][Hide abstract] ABSTRACT: In an irredundant sum-of-products expression (ISOP), each product is a prime implicant (Pl) and no product can be deleted without changing the function. Among the ISOPs for some function f, a worst ISOP (WSOP) is an ISOP with the largest number of Pls and a minimum ISOP (MSOP) is one with the smallest number. We show a class of functions for which the Minato-Morreale ISOP algorithm produces WSOPs. Since the ratio of the size of the WSOP to the size of the MSOP is arbitrarily large when it, the number of variables, is unbounded, the Minato-Morreale algorithm can produce results that are very far from minimum. We present a class of multiple-output functions whose WSOP size is also much larger than its MSOP size. For a set of benchmark functions, we show the distribution of ISOPs to the number of Pls. Among this set are functions where the MSOPs have almost as many Pls as do the WSOPs. These functions are known to be easy to minimize. Also, there are benchmark functions where the fraction of ISOPs that are MSOPs is small and MSOPs have many fewer Pls than the WSOPs. Such functions are known to be hard to minimize. For one class of functions, we show that the fraction of ISOPs that are MSOPs approaches 0 as n approaches infinity, suggesting that such functions are hard to minimize
[Show abstract][Hide abstract] ABSTRACT: The above paper finds an optimal fixed-polarity Reed-Muller expansion of an n-variable totally symmetric function using an OFDD-based algorithm that requires O(n/sup 7/) time and O(n/sup 6/) storage space. However, an algorithm based on Suprun's transient triangles requires only O(n/sup 3/) time and O(n/sup 2/) storage space. An implementation of this algorithm yields computation times lower by several orders of magnitude.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12/2000; 19(11-19):1386 - 1388. DOI:10.1109/43.892862 · 1.00 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We derive the average and worst case number of nodes in decision diagrams of r-valued symmetric functions of n variables. We show that, for large n, both numbers approach nr/rl. For binary decision diagrams (r=2), we compute the distribution of the number of functions on n variables with a specified number of nodes. Subclasses of symmetric functions appear as features in this distribution. For example, voting functions are noted as having an average of n2/6 nodes, for large n, compared to n2/2, for general binary symmetric functions
[Show abstract][Hide abstract] ABSTRACT: Multiple-output switching functions can be simulated by
multiple-valued decision diagrams (MDDs) at a significant reduction in
computation time. analyze the following approaches to the representation
problem: shared multiple-valued decision diagrams (SMDDs),
multi-terminal multiple-valued decision diagrams (MTMDDs), and shared
multi-terminal multiple-valued decision diagrams(SMTMDDs). For example,
we show that SMDDs fend to be compact, while SMTMDDs tend to be fast. We
present an algorithm for grouping input variables and output functions
in the MDDs
Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on; 06/1996
[Show abstract][Hide abstract] ABSTRACT: We show that a multiple-valued symmetric function has a planar
ROMDD (reduced ordered multiple-valued decision diagram) if and only if
it is a pseudo-voting function. We show that the number of such
functions is (r-1)(n+r, n+1) where r is the number of logic values and n
is the number of variables. It follows from this that the fraction of
symmetric multiple-valued functions that have planar ROMDDs approaches 0
as n approaches infinity. Further, we show that the worst case and
average number of nodes in planar ROMDDs of symmetric functions is
n<sup>2</sup>(1/2-1/2r) and n<sup>2</sup>(1/2-1/(r+1)), respectively,
when n is large
Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on; 06/1996
[Show abstract][Hide abstract] ABSTRACT: Direct and large eddy simulations of forced and decaying isotropic turbulence have been performed to investigate the behavior of subgrid models. Various subgrid models have been analyzed (i.e. Smagorinsky's eddy viscosity model, dynamic eddy viscosity model, dynamic one-equation model for the subgrid kinetic energy and scale-similarity model). A priori analysis showed that the subgrid stress and the subgrid energy flux predicted by the scale similarity model, and subgrid kinetic energy model (with fixed coefficients) correlate reasonably well with exact data, while the Smagorinsky's eddy viscosity model showed relatively poor agreement. However, the correlation for the scale similarity model decreased much more rapidly with decrease in grid resolution when compared to the subgrid kinetic energy model. The subgrid models were then used to carry out large-eddy simulations for a range of Reynolds number. When dynamic evaluation was incorporated, the correlation improved significantly. The dynamic subgrid kinetic energy model showed, consistently, a higher correlation for a range of Reynolds number when compared to the dynamic eddy viscosity model. These results demonstrate the capabilities of the dynamic one-equation model.
[Show abstract][Hide abstract] ABSTRACT: We propose the use of universal literals as a means of reducing
the cost of multiple-valued circuits. A universal literal is any
function on one variable. The target architecture is a sum-of-products
structure, where sum is the truncated sum and product terms consist of
the minimum of universal literals. A significant cost reduction is
demonstrated over the conventional window literal. The proposed
synthesis method starts with a sum-of-products expression.
Simplification occurs as pairs of product terms are merged and reshaped.
We show under what conditions such operations can be applied
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on; 06/1994
[Show abstract][Hide abstract] ABSTRACT: The performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the charge-coupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sum-of products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and random-symmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms
[Show abstract][Hide abstract] ABSTRACT: Minimal sum-of-products expressions for multiple-valued logic
functions for realization by programmable logic arrays are investigated.
The focus is on expressions where product terms consist of the MIN of
interval literals on input variables and are combined using one of two
operations, SUM or MAX. In binary logic, the question of whether or not
prime implicants are sufficient to realize all functions optimally has
been answered in the affirmative. The same question is considered for
higher radix functions. When the combining operation is MAX, prime
implicants are sufficient. However, it is shown that this is not the
case with SUM. It is also shown that all functions cannot be optimally
realized by successively selecting implicants that are prime with
respect to the intermediate functions. In fact, the number of implicants
in a solution using prime implicants successively can be significantly
larger than the number of implicants in a minimal solution
Multiple-Valued Logic, 1989. Proceedings., Nineteenth International Symposium on; 06/1989
[Show abstract][Hide abstract] ABSTRACT: The authors compare the performance of three heuristic algorithms for the minimization of sum-of-products expressions realized by the H.G. Kerkhoff and J.T. Butler's (1986) multiple-valued programmable logic arrays. Heuristic methods are important because exact minimization is extremely time-consuming. The authors compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. They use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions for which the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization.< >
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on; 06/1988
[Show abstract][Hide abstract] ABSTRACT: We introduce eigenfunctions of the Reed-Muller trans-form. Eigenfunctions are functions whose canonical sum-of-products expression and PPRM (positive polarity Reed-Muller expression) are isomorphic. In the case of symmet-ric functions, the eigenfunction can be viewed as a function whose reduced truth vector is identical to the reduced Reed-Muller spectrum. We show that the number of symmetric (ordinary) eigenfunctions on Ò-variables is ¾ Ò·½ ¾ (¾ ¾ Ò½).