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ABSTRACT: Using first-principles calculations we investigated the oxidation properties of model Pt/HfO2 interfaces as a function of oxygen partial pressure. A wide range of interfacial oxygen concentrations were explored, varying from an oxygen-free interface to the case of 1 oxygen ML separating the Pt(111) slab from the first Hf plane in the monoclinic HfO2(001) slab. In all cases the interfaces were optimized using ab initio molecular dynamics. It was found that 1 ML of oxygen at the Pt/HfO2 interface is only possible for chemical potentials equivalent to an oxygen pressure of tens of bars. With respect to silicon oxidation only the oxygen-free interface is stable. Depending on the anneal conditions, intermediate concentrations of ~0.25 or ∼ 0.75 ML of oxygen at the interface are possible, while the concentration of 0.5 ML is only stable over a narrow range of conditions. The band offset and work of separation were calculated for Pt/HfO2 interfaces as a function of the oxygen concentration at the interface. The valence band offset drops sharply with increasing oxygen chemical potential, from ∼ 3.0 to ∼ 1.0 eV. The same trend is observed for the work of separation, which decreases from ∼ 6 J/m2 for an oxygen-free interface to ∼ 1 J/m2 for one oxygen monolayer. These findings may shed new light into recent experimental data reporting exceedingly small values for the effective work function of Pt on HfO2 and its dependence on the oxygen partial pressure during high temperature annealing.
Journal of Applied Physics 01/2007; 101(1):014310-014310-7. · 2.17 Impact Factor
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A.V.-Y. Thean,
A. Vandooren,
S. Kalpat,
Y. Du,
I. To,
J. Hughes,
T. Stephens,
B. Goolsby,
T. White,
A. Barr, [......],
M. Rossow,
D. Roan,
D. Pham,
R. Rai,
S. Murphy,
B.-Y. Nguyen,
B.E. White,
A. Duvallet,
T. Dao,
J. Mogab
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ABSTRACT: In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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W.J. Taylor,
E. Verret,
C. Capasso,
Jen-Yee Nguyen,
Le Boi La,
E. Luckowski,
A Martinez,
C. Happ, J Schaeffer,
M Raymond,
P. Tobin
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ABSTRACT: It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.
Junction Technology, 2004. IWJT '04. The Fourth International Workshop on; 04/2004
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Bich-Yen Nguyen,
A. Thean,
T. White,
A. Vandooren,
M. Sadaka,
L. Mathew,
A. Barr,
S. Thomas,
M. Zalava,
Da Zhang, [......],
S. Kalpat,
L. Prabhu,
V. Kaushik,
Y. Du,
T. Dao,
M. Mendicino,
M. Orlowski,
P. Tobin,
J. Mogab,
S. Venkatesan
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ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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A. Vandooren,
A.V.Y. Thean,
Y. Du,
I. To,
J. Hughes,
T. Stephens,
M. Huang,
S. Egley,
M. Zavala,
K. Sphabmixay, [......],
M. Rossow,
D. Roan,
D. Pham,
R. Rai,
B.-Y. Nguyen,
B. White,
M. Orlowski,
A. Duvallet,
T. Dao,
J. Mogab
[show abstract]
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ABSTRACT: We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO<sub>2</sub> dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20Å. The intrinsic low-leakage nature of the FDSOI device and it's immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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S.B. Samavedam,
L.B. La,
P.J. Tobin,
B. White,
C. Hobbs,
L.R.C. Fonseca,
A.A. Demkov, J. Schaeffer,
E. Luckowski,
A. Martinez, [......],
R. Garcia,
S.G.H. Anderson,
K. Moore,
H.H. Tseng,
C. Capasso,
O. Adetutu,
D.C. Gilmer,
W.J. Taylor,
R. Hegde,
J. Grant
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ABSTRACT: We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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A. Vandooren,
S. Egley,
M. Zavala,
T. Stephens,
L. Mathew,
M. Rossow,
A. Thean,
A. Barr,
Z. Shi,
T. White,
D. Pham,
J. Conner,
L. Prabhu,
D. Triyoso, J. Schaeffer,
D. Roan,
Bich-Yen Nguyen,
M. Orlowski,
J. Mogab
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ABSTRACT: In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO<sub>2</sub> gate dielectric at the 50-nm physical gate length. Symmetric V<sub>T</sub> is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I<sub>on</sub>=500 μA/μm and I<sub>off</sub>=10 nA/μm at V<sub>DD</sub>=1.2 V for nMOSFET and I<sub>on</sub>=212 μA/μm and I<sub>off</sub>=44 pA/μm at V<sub>DD</sub>=-1.2 V for pMOSFET, with a CET=30 Å and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V<sub>DD</sub>=1.2 V are also realized.
IEEE Transactions on Nanotechnology 01/2004; · 2.29 Impact Factor
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A. Vandooren,
A. Barr,
L. Mathew,
T.R. White,
S. Egley,
D. Pham,
M. Zavala,
S. Samavedam, J. Schaeffer,
J. Conner,
B.-Y. Nguyen,
B.E. White Jr,
M.K. Orlowski,
J. Mogab
[show abstract]
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ABSTRACT: We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.
IEEE Electron Device Letters 06/2003; · 2.85 Impact Factor
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A. Vandooren,
S. Egley,
M. Zavala,
A. Franke,
A. Barr,
T. White,
S. Samavedam,
L. Mathew, J. Schaeffer,
D. Pham,
J. Conner,
S. Dakshina-Murthy,
B.-Y. Nguyen,
B. White,
M. Orlowski,
J. Mogab
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ABSTRACT: We report for the first time physical and electrical characterization of ultra-thin (<100-150A) Fully-Depleted Silicon-On-Insulator (SOI) n and pMOSFETs using TaSiN gate and HfO<sub>2</sub> dielectric with elevated Source/Drain extensions.
SOI Conference, IEEE International 2002; 11/2002
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S.B. Samavedam,
H.H. Tseng,
P.J. Tobin,
J. Mogab,
S. Dakshina-Murthy,
L.B. La,
J. Smith, J. Schaeffer,
M. Zavala,
R. Martin, [......],
M. Moosa,
D.C. Gilmer,
C. Hobbs,
W.J. Taylor,
J.M. Grant,
R. Hegde,
S. Bagchi,
E. Luckowski,
V. Arunachalam,
M. Azrak
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ABSTRACT: We report for the first time electrical characterization of HfO<sub>2</sub> p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO<sub>2</sub> and SiO<sub>2</sub> n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA/μm leakage, 0.345 mA/μm drive current was obtained from PVD TiN/HfO<sub>2</sub> p-MOSFETs. HfO<sub>2</sub> n-MOSFETs with metal gates show about 10<sup>4</sup> times reduction in gate leakage compared to poly/SiO<sub>2</sub> devices.
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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S.B. Samavedam,
L.B. La,
J. Smith,
S. Dakshina-Murthy,
E. Luckowski, J. Schaeffer,
M. Zavala,
R. Martin,
V. Dhandapani,
D. Triyoso, [......],
J. Mogab,
C. Thomas,
P. Abramowitz,
M. Moosa,
J. Conner,
J. Jiang,
V. Arunachalarn,
M. Sadd,
B.-Y. Nguyen,
B. White
[show abstract]
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ABSTRACT: We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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Antennas and Propagation Society International Symposium, 1979; 07/1979
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L. Mathew,
M. Sadd,
B.E. White,
A. Vandooren,
S. Dakshina-Murthy,
J. Cobb,
T. Stephens,
R. Mora,
D. Pham,
J. Conner, [......],
Z. Shi,
A.V.-Y. Thean,
A. Barr,
M. Zavala, J. Schaeffer,
M.J. Rendon,
D. Sing,
M. Orlowski,
B.-Y. Nguyen,
J. Mogab
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ABSTRACT: A vertical double gate MOSFET structure with a new gate stack architecture has been demonstrated. The gate stack consists of two isolated polysilicon regions that are doped N+ and P+ with a metal/polysilicon strap connecting the doped regions. The device has an undoped channel yet performs as an enhancement mode MOSFET due to the asymetric doping of the gate regions on either side of the channel. The advantages of this structure include: 1) reduction of the Vt variations caused by dopant fluctuation in the channel region; 2) enhanced mobility due to an undoped channel region; 3) flexibility to adjust Vt across a wide range from depletion mode to very high Vt depending on the application; 4) lower interconnect resistance due to the use of metal/polysilicon gate components; 5) better manufacturability due to easier patterning of gate over spacer. The devices are enhancement mode with Vt ∼=(0.1-0.3V) at 100 nm gate length and channel thickness of less than 30 nm gate length and height 100 nm tall have been demonstrated. Functional devices at the 100 nm gate have Ion=191 μA/μm, Vt=0.3 V Ioff =0.5 μA/μm, SS=94 mV/decade. A different device with different implant dose and drive demonstrated Vt=0.15 V and SS=80mV/decade at Lgate=0.25 μm.
SOI Conference, 2003. IEEE International;
