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Publications (36)37.02 Total impact

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    ABSTRACT: Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high- k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si<sub>1 -</sub> x Ge x channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high- k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si<sub>1 -</sub> x Ge x thicknesses, boron counterdopings, and gate work functions.
    IEEE Transactions on Electron Devices 05/2010; · 2.06 Impact Factor
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    ABSTRACT: One method to further scale hafnium based dielectrics is to stabilize the tetragonal phase of HfO2 via zirconium addition. In this paper we investigated factors impacting stabilization of tetragonal phase in thin HfxZr1-xO2 high-k dielectrics such as deposition technique, precursor combination, annealing ambient and the use of capping layers.
    01/2009;
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    ABSTRACT: The impact of ultrathin metal underlayer on physical and electrical properties of Hf <sub>x</sub> Zr<sub>1-</sub> <sub>x</sub> O<sub>2</sub>(x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf <sub>x</sub> Zr<sub>1-</sub> <sub>x</sub> O<sub>2</sub> growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high- k film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.
    IEEE Electron Device Letters 02/2008; · 2.79 Impact Factor
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    ABSTRACT: Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta<sub>x</sub>C<sub>y</sub>/HfZrO<sub>x</sub>/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.
    IEEE Transactions on Electron Devices 01/2008; · 2.06 Impact Factor
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    ABSTRACT: TaCy has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on the development and characterization of a novel TaCy process by atomic layer deposition (ALD). Detailed physical properties of TaCy films are studied using ellipsometry, a four-point probe, Rutherford backscattering spectrometry (RBS), x-ray photoelectron spectroscopy (XPS), and x-ray diffraction (XRD). RBS and XPS analysis indicate that TaCy films are near-stoichiometric, nitrogen free, and have low oxygen impurities. Powder XRD spectra showed that ALD films have a cubic microstructure. XPS carbon bonding studies revealed that little or no glassy carbon is present in the bulk of the film. Excellent electrical properties are obtained using ALD TaCy as a metal gate electrode. Well-behaved capacitance-voltage characteristics with ALD HfO2 gate dielectrics are demonstrated for TaCy thicknesses of 50, 100, and 250 Å. A low fixed charge ( ∼ 2–4×10−11 cm−2) is observed for all ALD HfO2/ALD TaCy devices. Increasing the thickness of ALD TaCy results in a decrease in work function (4.77 to 4.54 eV) and lower threshold voltages.
    Journal of Applied Physics 11/2007; 102(10):104509-104509-4. · 2.21 Impact Factor
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    ABSTRACT: Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.
    Journal of Applied Physics 10/2007; 102(7):074511-074511-5. · 2.21 Impact Factor
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    ABSTRACT: Using first-principles calculations we investigated the oxidation properties of model Pt/HfO2 interfaces as a function of oxygen partial pressure. A wide range of interfacial oxygen concentrations were explored, varying from an oxygen-free interface to the case of 1 oxygen ML separating the Pt(111) slab from the first Hf plane in the monoclinic HfO2(001) slab. In all cases the interfaces were optimized using ab initio molecular dynamics. It was found that 1 ML of oxygen at the Pt/HfO2 interface is only possible for chemical potentials equivalent to an oxygen pressure of tens of bars. With respect to silicon oxidation only the oxygen-free interface is stable. Depending on the anneal conditions, intermediate concentrations of ~0.25 or ∼ 0.75 ML of oxygen at the interface are possible, while the concentration of 0.5 ML is only stable over a narrow range of conditions. The band offset and work of separation were calculated for Pt/HfO2 interfaces as a function of the oxygen concentration at the interface. The valence band offset drops sharply with increasing oxygen chemical potential, from ∼ 3.0 to ∼ 1.0 eV. The same trend is observed for the work of separation, which decreases from ∼ 6 J/m2 for an oxygen-free interface to ∼ 1 J/m2 for one oxygen monolayer. These findings may shed new light into recent experimental data reporting exceedingly small values for the effective work function of Pt on HfO2 and its dependence on the oxygen partial pressure during high temperature annealing.
    Journal of Applied Physics 01/2007; 101(1):014310-014310-7. · 2.21 Impact Factor
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    ABSTRACT: The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta/(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitrogen atom. This result is in qualitative agreement with the known relationship between metal electronegativity and effective work function and demonstrates the important role that sublattice elements in binary metal compounds have on the effective work function of the gate electrode.
    Journal of Applied Physics 01/2007; 101(1):014503-014503-9. · 2.21 Impact Factor
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    ABSTRACT: In this study, the authors investigated the addition of zirconium (Zr) into HfO2 to improve its dielectric properties. HfxZr1-xO2 films were deposited by atomic-layer deposition at 200–350 °C and annealed in a nitrogen ambient environment at 1000 °C. Extensive physical characterization of the impact of alloying Zr into HfO2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. HfxZr1-xO2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO2 leads to changes in film microstructure and grain-size distribution. HfxZr1-xO2 films have smaller and more uniform grain size compared to HfO2 for all deposition temperatures explored here. As Zr content and deposition temperature are increased, stabilization of the tetragonal phase is observed. A monotonic decrease in band gap is observed as ZrO2 content is increased. The chlorine impurity in the films is strongly dependent on deposition temperature and independent of film composition. TEM images of transisto- - rs showed excellent thermal stability as revealed by a sharp HfxZr1-xO2/Si interface and no Zr silicide formation. Significant improvement in device properties such as lower electrical thickness (higher permittivities), lower threshold voltage (Vt) shift after stress (improved reliability), and higher mobilities are observed with Zr addition into HfO2. All of these results show HfxZr1-xO2 to be a promising candidate for SiO2 replacement.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 01/2007; 25(3):845-852. · 1.36 Impact Factor
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    ABSTRACT: The empirical relationship between electronegativity and effective work function is applied to a diverse set of multi-element electrode materials on hafnium dioxide (HfO2) gate dielectrics. To accommodate the multi-element nature of metal gate electrodes the group electronegativity of the metal was calculated from the geometric mean of electronegativity with respect to the volume stoichiometry of the constituent elements. Results show a reasonable linear fit that provides guidance for the selection of metal gate electrodes on HfO2. The group electronegativity concept is also extended to work function engineering via dielectric capping materials. The electronegativity trends provide insight into the relative charge neutrality levels of candidate dielectric capping materials and their subsequent impact on the metal effective work function.
    Microelectronic Engineering 01/2007; 84(s 9–10):2196–2200. · 1.22 Impact Factor
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    ABSTRACT: In this paper, various approaches to extend scalability of Hafnium-based dielectrics are reported. Among the three crystal phases of HfO2 (monoclinic, cubic and tetragonal), the tetragonal phase has been reported to have the highest dielectric constant. Tetragonal phase stabilization by crystallizing the thin HfO2 using a metal capping layer and by adding zirconium is demonstrated. The microstructure, morphology, optical properties and impurities of HfxZr1-xO2 dielectrics (for 0<x<1) are discussed. Subtle but important modification to high-k / Si interface characteristics resulting from addition of Zr into HfO2 is reported. To further boost the dielectric constant of hafnium-based dielectrics, incorporation of TiO2, which has been reported to have high dielectric constant, is explored. HfxZr1-xO2/TiO2 bilayer films were fabricated. 30 Å TiO2 films were deposited on a 5, 8, 12 or 15 Å HfxZr1-xO2 underlayer to determine the minimum thickness needed to maintain good thermal stability with Si substrate. CV and IV results indicated that 12-15 Å is the optimal thickness range for the HfxZr1-xO2 underlayer. A dielectric constant as high as 150 for TiO2 layer is extracted from TiO2 thickness series deposited on12 Å HfxZr1-xO2 underlayer. In addition to increasing the k-value of Hafnium-based dielectrics, it is important that the threshold voltage of these high-k devices is low. Here we report the use of thin Al2O3 capping layers to modulate PMOS threshold voltages. About 100 mV reduction in threshold voltage is achieved by capping HfO2 with a 5Å Al2O3 film. Finally, dielectric scaling by modifying the Si/high-k interfacial layer is attempted. Nitrogen incorporation into HfxZr1-xO2 is shown to be a simple and effective method to lower the capacitance equivalent thickness (CET) of Hafnium-based dielectrics.
    MRS Proceedings. 12/2006; 996.
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    ABSTRACT: For the first time, we report on the beneficial result for minimizing the activation thermal budget using LASER anneals with metal-oxide-gate-electrode/high-k dielectric MOSFETs. With LASER activation, EOT for PMOS conductive metal-oxide gated devices is reduced 4-5Aring compared to conventional RTP activation methods leading to more aggressive ultimate CMOS scaling when using a conductive metal-oxide for the PMOS gate electrode
    Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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    ABSTRACT: The impact of Zr addition on microstructure of HfO2 after high temperature processing was investigated using Rutherford backscattering, x-ray diffraction (XRD), transmission electron microscopy, and atomic force microscopy (AFM). The ZrO2 content in the films was varied from ∼ 25% to 75%. XRD analysis shows that adding >50% ZrO2 leads to partial stabilization of tetragonal phase of the HfxZr1−xO2 alloy. AFM images revealed smaller grains with Zr addition. Conducting AFM showed more uniform and tighter tunneling current distribution in HfxZr1−xO2 compared to HfO2. Constant capacitance-voltage stressing performed on HfO2 and HfxZr1−xO2 metal-oxide-semiconductor capacitors indicated reduced charge trapping with Zr addition.
    Applied Physics Letters 05/2006; 88(22):222901-222901-3. · 3.79 Impact Factor
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    ABSTRACT: Fermi level pinning at the Re/HfO2 interface and its contribution to the Re interface work function in the Re/HfO2/SiOx/n-Si stack were investigated using x-ray and ultraviolet photoelectron spectroscopy in conjunction with capacitance-voltage (C-V) measurements. Photoemission results showed that the Fermi level was partially pinned at the Re/HfO2 interface, resulting in a 0.5 eV interface dipole and 5.0 eV interface work function between Re and HfO2. In contrast, C-V measurement of the Re/HfO2/SiOx/n-Si stack showed a 4.7–4.8 eV interface work function. The difference in Re interface work functions is discussed in terms of contributions of additional interface dipoles in the stack.
    Applied Physics Letters 02/2006; 88(7):072907-072907-3. · 3.79 Impact Factor
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    ABSTRACT: Not Available
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: Using a novel fluorinated Ta<sub>x</sub>C<sub>y</sub>/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2006
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    ABSTRACT: A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI
    01/2006;
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    ABSTRACT: In this article, we evaluated physical and electrical characteristics of La-based gate dielectrics ( La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> ) deposited by atomic layer deposition (ALD). The precursors used for La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> are lanthanum tris[bis(trimethylsilyl)amide] La [ N ( Si Me <sub>3</sub>)<sub>2</sub>]<sub>3</sub> , trimethyl aluminum [ Al ( CH <sub>3</sub>)<sub>3</sub>] , and water. Physical properties of these dielectric films were studied using ellipsometry, x-ray photoelectron spectroscopy (XPS), and transmission electron microscopy (TEM). To investigate electrical properties of these La-based dielectrics, metal oxide semiconductor capacitors (MOSCAPs) were fabricated using metal gates (Ta–Si–N, TiN and Pt). Linear growth rate characteristics were observed for ALD ( La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> films deposited at temperatures of 225 to 275 ° C . XPS and XTEM analysis of La-based films grown on a chemical oxide starting surface revealed a rough La-based dielectric/Si interface and chemical interaction with the Si substrate. In general, adding Al into La <sub>2</sub> O <sub>3</sub> improved electrical properties of the films. Devices with La based dielectric deposited on a ∼10 Å Al <sub>2</sub><rom- - an>O <sub>3</sub> underlayer had better capacitance-voltage characteristics compared to those deposited directly on a chemical oxide surface. Adding Al to the dielectric also resulted in lower leakage current and smaller hysteresis. For devices with Ta–Si–N gates, a significant decrease in maximum capacitances was observed after forming gas annealing, probably due to interaction between the gate electrode and the dielectric. XTEM images for these devices indicated an indistinct interface between the Ta–Si–N gate and the La-based dielectrics. The XTEM images also showed microcrystals in Ta–Si–N that may be formed in Si deficient regions of the metal gate. No interaction between TiN or Pt with La gate dielectrics was observed by XTEM up to 800 ° C annealing temperature. After 900 ° C annealing, some interaction between La Al <sub>x</sub> O <sub>y</sub> and Pt gate was observed. Our results indicated that silicon substrate interactions may limit the utilization of ALD La based dielectrics in future complementary metal-oxide semiconductor processing.
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 02/2005; · 1.36 Impact Factor
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    ABSTRACT: Threshold voltage instability is a critical problem for high-K dielectric implementation. This problem is much more serious for short channel devices due to process induced gate edge damage. A novel stress relieved pre-oxide (SRPO) followed by ALD of HfO<sub>2</sub> reduces the local charge density near the gate edge and short channel threshold voltage instability. Excellent cross wafer CETinv uniformity is achieved for the SRPO process. A new tantalum carbon alloy metal gate achieves a lower Vtsat than TaSiN gated devices due to a lower work function. Compared to HfO<sub>2</sub>/TaSiN devices using standard RCA pre-clean, HfO<sub>2</sub>/tantalum carbon alloy metal gate stack using the novel SRPO demonstrates a 3× smaller Vt shift for short channel devices and a 16% Ion/Ioff improvement.
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005