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K. Cheng,
A. Khakifirooz,
P. Kulkarni,
S. Kanakasabapathy,
S. Schmitz,
A. Reznicek,
T. Adam,
Y. Zhu, J. Li,
J. Faltermeier, [......],
T. Levin,
M. Smalley,
J. Herman,
M. Di,
J. Wang,
D. Sadana,
P. Kozlowski,
H. Bu,
B. Doris,
J. O'Neill
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ABSTRACT: A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200 Omegaldrm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2 nm ETSOI. Even without strain boosters, a remarkable PFET drive current of 550 muA/mum is achieved at I<sub>off</sub> = 3nA/mum, V<sub>DD</sub> = 0.9 V with 6 nm SOI channel and 25 nm physical gate length. Shortchannel effects are well-controlled with DIBL less than 100 mV/V and subthreshold swing less than 90 mV/dec. A 15% reduction in parasitic capacitance is achieved by a faceted raised source/drain (RSD). Excellent electrostatics and small device dimensions render ETSOI devices suitable for 22-nm node and beyond.
VLSI Technology, 2009 Symposium on; 07/2009
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B. Yang,
R. Takalkar,
Z. Ren,
L. Black,
A. Dube,
J.W. Weijtmans, J. Li,
J.B. Johnson,
J. Faltermeier,
A. Madan, [......],
S. Zollner,
P. Grudowski,
D. Sadana,
D.-G. Park,
D. Mocuta,
D. Schepis,
E. Maciejewski,
S. Luning,
J. Pellerin,
E. Leobandung
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ABSTRACT: For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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Zhibin Ren,
G. Pei, J. Li,
B.F. Yang,
R. Takalkar,
K. Chan,
G. Xia,
Z. Zhu,
A. Madan,
T. Pinto, [......],
L. Black,
J.W. Weijtmans,
B. Yang,
E. Harley,
A. Chakravarti,
T. Kanarsky,
R. Pal,
I. Lauer,
D.-G. Park,
D. Sadana
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ABSTRACT: We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (C<sub>sub</sub>) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced I<sub>eff</sub> and ~15% improved I<sub>dlin</sub> against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.
VLSI Technology, 2008 Symposium on; 07/2008
