J Klein

Publications (3)0 Total impact

• Conference Proceeding: Interconnect material and CMP process change effects on local interconnect planarity

  J. Mendonca, C. Dang, C. Pettinato, J. Cope, H. Garcia, J. Saravia, J. Farkas, D. Watts, J. Klein
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  ABSTRACT: With finer geometries and multiple metal levels, CMP planarity demands have increased at the lower device levels. Interconnect material changes (metals such as W, Ti, TiN and dielectrics such as BP-TEOS, HDP, and F-HDP) and CMP process changes (such as pads and tool sets) were explored to improve the post-polish planarity at the local interconnect level. The pad hardness was found to offer the best avenue, with up to a tenfold decrease in the post-CMP interlevel dielectric thickness range
  Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International; 07/1998
• Conference Proceeding: Integration of multi-level copper metallization into a highperformance sub-0.25 μm CMOS technology

  S. Venkatesan, R. Venkatraman, A Jain, J. Mendonca, S Anderson, M. Angyal, C. Capasso, J. Cope, P. Crabtree, S Das, [......], J Klein, T. Lii, V. Misra, K. Reid, C. Simpson, B Smith, T. Sparks, D. Watts, E.J. Weitzman, B. Wilson
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  ABSTRACT: A high performance sub-0.25 μm CMOS technology has been developed with six levels of planarized copper interconnects. 0.15 μm transistors (L_gate=0.15 μm) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects to minimize wiring induced RC delays
  Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on; 04/1998
• Conference Proceeding: A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization

  S. Venkatesan, A.V. Gelatos, S. Hisra, B. Smith, R. Islam, J. Cope, B. Wilson, D. Tuttle, R. Cardwell, S. Anderson, [......], T. Sparks, P. Tsui, R. Venkatraman, D. Watts, E.J. Weitzman, R. Woodruff, I. Yang, N. Bhat, G. Hamilton, Y. Yu
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  ABSTRACT: A high performance 0.20 μm logic technology has been developed with six levels of planarized copper interconnects. 0.15 μm transistors (L_gate=0.15±0.04 μm) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized and enable fabrication of 7.6 μm ² 6T SRAM cells
  Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998