W.C. Natzle,
D. Horak,
S. Deshpande,
Chien-Fan Yu,
J.C. Liu,
R.W. Mann,
B. Doris,
H. Hanafi,
J. Brown,
A. Sekiguchi, [......],
P. Cottrell,
F. Higuchi, H. Takahashi,
M. Sendelbach,
E. Solecky,
Wendy Yan,
L. Tsou,
Qingyun Yang,
J.P. Norum,
S.S. Iyer
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ABSTRACT: A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop; 06/2004
