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ABSTRACT: We investigate the electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. For this purpose, we perform simulations using a physical model that reproduces the charge injection/trapping in TANOS devices, which is extended in order to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase, and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in an accelerated charge loss.
Journal of Applied Physics 01/2011; 110:014505. · 2.17 Impact Factor
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Microelectronic Engineering 01/2011; 88(7):1255-1258. · 1.56 Impact Factor
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ABSTRACT: An attempt is made to correlate electrical measurement results to specific defects in the dielectric stacks of high-k/metal gate devices. Defect characteristics extracted from electrical data were compared to those obtained by ab initio calculations of the dielectric structures. It is demonstrated that oxygen vacancies in a variety of charge states and configurations in the interfacial SiO2 layer of the high-k gate stacks contribute to random telegraph noise signal, time-dependent dielectric breakdown, and the flatband voltage roll-off phenomenon.
International Journal of High Speed Electronics and Systems 01/2011; 20(1):65.
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ABSTRACT: The presented theoretical analysis of random telegraph signal (RTS) and 1/f noise data provides consistent interpretation of the measurement results allowing trap characteristics to be extracted and the atomic structure of oxide traps to be identified. We emphasize the critical role of the lattice structural relaxation associated with charge trapping/detrapping, which represents one of the major factors controlling electron capture/emission times.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: As CMOS trends continue to scale for future technology nodes, three-dimensional (3D) multi-gate field effect transistors (MugFETs) could be a viable approach. One type of MugGET of particular interest is the FinFET in which a silicon fin is defined on a buried oxide (BOX) layer. The FinFET is attractive because it is compatible with conventional CMOS processing. However, due to the crystal orientation of the fin sidewalls, their interface with the gate dielectric may contain more interface states, as well as be more sensitive to stress-induced degradation than planar devices. Therefore, these interface states and their impact on longterm operation must be characterized. FinFETs on BOX, however, do not have a substrate contact for traditional interface state characterization methods. To circumvent this issue, a gated diode FinFET test structure can be used, which emulates a planar device configuration allowing interface characterization techniques such as charge pumping (CP) and DC gated-diode current-voltage (DCIV) measurements. To determine which technique best characterizes sidewall interfaces; CP and DCIV measurements were used to monitor the time evolution of interface state generation and oxide charging during bias temperature instability (BTI) tests of the gated diode FinFETs.
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on; 05/2010
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D.C. Gilmer,
N. Goel, H. Park,
C. Park,
S. Verma,
G. Bersuker,
P. Lysaght,
H.-H. Tseng,
P.D. Kirsch,
K.C. Saraswat,
R. Jammy
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ABSTRACT: We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiN<sub>x</sub> charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiN<sub>x</sub>, BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ¿Vth P/E windows of > 300%, enduring P/E cycles to at least 100 K cycles while maintaining a window > 4 V, and retention approaching zero% charge loss over 24 hours at 150°C. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30 nm node.
Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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H. Park,
G. Bersuker,
D. Gilmer,
K. Y. Lim,
M. Jo,
H. Hwang,
A. Padovani,
L. Larcher,
P. Pavan,
W. Taylor,
P. D. Kirsch
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ABSTRACT: In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time is decreased down to micro seconds. Blocking oxides engineered by adding a thin SiO2 layer at the SiN/AlO interface demonstrate significant suppression of the charge loss.
IEEE International Memory Workshop, Seoul, Korea; 01/2010
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G. Bersuker,
D. C. Gilmer,
D. Veksler,
J. Yum, H. Park,
S. Lian,
L. Vandelli,
A. Padovani,
L. Larcher,
K. McKenna,
A. Shluger,
V. Iglesias,
M. Porti,
M. Nafría,
W. Taylor,
P. D. Kirsch,
R. Jammy
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ABSTRACT: By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).
IEEE International Electron Devices Meeting, San Francisco, California; 01/2010
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Solid State Technology 01/2010; 53(6):21-25. · 0.27 Impact Factor
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IEEE Electron Device Letters 01/2010; 31(7):653-655. · 2.85 Impact Factor
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H Park,
G Bersuker,
M Jo,
D Veksler,
KY Lim,
D Gilmer,
N Goel,
CY Kang,
C Young,
M Chang,
others
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on; 01/2010
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J. Huang,
D. Heh,
P. Sivasubramani,
P.D. Kirsch,
G. Bersuker,
D.C. Gilmer,
M.A. Quevedo-Lopez,
M.M. Hussain,
P. Majhi,
P. Lysaght, [......],
N. Goel,
C. Young,
C.S. Park,
C. Park,
M. Cruz,
V. Diaz,
P.Y. Hung,
J. Price,
H.-H. Tseng,
R. Jammy
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ABSTRACT: Gate first 0.59 nm EOT HfO<sub>x</sub>/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfO<sub>x</sub> deposition, ldquozerordquo low-k SiO<sub>x</sub> interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL HfO<sub>x</sub> vs. exotic higher-k. Transistors made with ZIL HfO<sub>x</sub> show good interfaces (SS=70-80 mV/dec, N<sub>it</sub> = 5 times 10<sup>10</sup>/cm<sup>2</sup>) and performance (10% I<sub>on</sub>-I<sub>off</sub> boost vs. EOT = 0.95 nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfO<sub>x</sub> are discussed.
VLSI Technology, 2009 Symposium on; 07/2009
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ABSTRACT: We demonstrate for the first time molybdenum based oxygen-bearing electrodes for improved performance in MANOS (Metal-Alumina-Nitride-Oxide) charge-trap NVM, and also MIM-DRAM type devices. The meta-stable high work- function (Wfn) molybdenum-oxynitride (MoON) electrodes result in improved retention and erase saturation for the charge trap NVM devices and improved leakage for the MIM devices. Although some of the observed improvements, compared to conventional TaN or TIN electrodes, can be attributed to the higher effective Wfn of the MoON, the improvements are also attributed to free oxygen available during deposition, and also released from the MoON electrode during thermal processing, repairing defects in the respective dielectrics adjacent to the MoON electrodes.
Memory Workshop, 2009. IMW '09. IEEE International; 06/2009
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ABSTRACT: The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al<sub>2</sub>O<sub>3</sub>-Si<sub>3</sub>N<sub>4</sub>-SiO<sub>2</sub>-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN<sub>x</sub> trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaV<sub>t</sub> = 4V with respect to the initial state are obtained. The band-engineered SiN<sub>x</sub> charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.
IEEE Electron Device Letters 04/2009; · 2.85 Impact Factor
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G. Bersuker,
D. Heh,
C. Young, H. Park,
P. Khanal,
L. Larcher,
A. Padovani,
P. Lenahan,
J. Ryan,
B.H. Lee,
H. Tseng,
R. Jammy
[show abstract]
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ABSTRACT: We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO<sub>2</sub> interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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Integrated Reliability Workshop Final Report, 2009. IRW'09. IEEE International; 01/2009
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S. Verma,
G. Bersuker,
D. C. Gilmer,
A. Padovani, H. Park,
A. Nainani,
D. Heh,
J. Huang,
J. Jiang,
K. Parat,
P. D. Kirsch,
L. Larcher,
H.-H. Tseng,
K. C. Saraswat,
R. Jammy
[show abstract]
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ABSTRACT: We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Qbd) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node.
IEEE International Memory Workshop, Monterey, California (USA); 01/2009
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S. Verma,
G. Bersuker,
D. C. Gilmer,
A. Padovani, H. Park,
A. Nainani,
J. Huang,
K. Parat,
P. D. Kirsch,
L. Larcher,
H.-H. Tseng,
K. C. Saraswat,
R. Jammy
6th International Symposium on Advanced Gate Stack Technology, San Francisco, California; 01/2009
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Advanced Workshop on 'Frontiers in Electronics' (WOFE 2009), Puerto Rico; 01/2009
