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ABSTRACT: This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated for the design of an half-bridge Class-D loop filter topology for portable applications that achieves less than 0.005% THD at 340mW output power with a 3.3V supply in typical 0.18um CMOS technology.
Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on; 11/2010
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ABSTRACT: This paper addresses the analog integrated circuit design automation by proposing an innovative circuit-level optimization kernel. The proposed approach, first, models analog design knowledge using soft computing techniques, than, enhances a stochastic optimization kernel by embedding the design knowledge model. The proposed approach uses common IC design environments and is validated for well known design examples.
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on; 09/2009
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ABSTRACT: This paper presents a multi-standard reconfigurable sigma-delta modulator, which is able to support the predictable standards of fourth generation of mobile communication systems (4G). Furthermore, the proposed architecture halves the number of required analog-to-digital converters in parallel receivers, by processing concurrently two different signals. The major design issues are outlined and operation modes are detailed. A system-level simulation is performed to demonstrate the feasibility of the presented solution.
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
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ABSTRACT: In this paper a new design automation approach to the problem of sizing analog ICs is described. The proposed approach employs a dynamic learning scheme, based on Support Vector Machines (SVMs), which together with an evolutionary strategy is used to create feasibility models to efficiently prune the design search space during the optimization process. The proposed approach is demonstrated for the design of CMOS operational amplifiers.
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
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ABSTRACT: This paper presents a circuit/system level synthesis and optimization approach based on a learning scheme using support vectors machines (SVMs) and evolutionary strategies applied to the design of analog and mixed-signal ICs. This approach combines the best qualities of these two techniques, a robust classification and regression method and a powerful global optimization. The SVM is used to dynamically model performance space and identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization-based approach is demonstrated for the design of some analog circuits using HSPICE as the evaluation engine.
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on; 01/2007
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ABSTRACT: This paper presents a new design automation methodology for analog IC design. The proposed approach introduces an increased level of flexibility and reusability when compared to traditional approaches. The flexibility is achieved by allowing the designer to define both his/her own hierarchical design organization and, simultaneously, the design flow for each design level. The reusability is achieved by introducing a highly organized data structure, to store the entire design data, allowing an easy reuse of designed systems and predefined design flows. Finally, a case study is presented to illustrate the implementation of the described design automation methodology.
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on; 08/2005
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ABSTRACT: This paper presents a new evolutionary optimization kernel applied to the automatic synthesis of high performance analog and mixed-signal ICs. This enhanced evolutionary approach is based on a modified genetic algorithm with self adaptive parameters tailored to efficiently control the optimization process. Particularly, the benefits introduced by self adaptive parameters consist of, first, reducing the problem complexity by using a grid with an adaptive resolution or step to describe the search space, then, improving the circumvention of local minima by including an adaptive mutation operator. The enhanced optimization kernel were tested for a broad range of well known test functions and compared to other approaches using MATLAB. Finally, the proposed optimization-based approach is demonstrated for the design of high-performance differential amplifiers using HSPICE as the evaluation engine.
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on; 08/2005
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ABSTRACT: ADSL (asymmetrical digital subscriber line) applications requires ADCs with wide dynamic input range, of up to 80 dB. The modulation method employed, 14 bit QAM only needs about 42 dB of signal-to noise ratio (SNR) to achieve a BER of 10<sup>-8</sup>. This suggest that a converter with a nonlinear characteristic that achieves an SNR of 42 dB and a dynamic range of 80 dB can be used in this type of applications with the advantage of the reduced number of bits. A logarithmic converter has also the advantage that the output SNR is independent of the statistics of the input signal. The proposed converter is a true logarithmic pipeline architecture, with 9 bits and 80 dB dynamic range. This converter processes the input signal in the same way as a linear converter but in the logarithmic domain. This paper describes the design of a logarithmic pipeline A/D converter that meet the ADSL requirements, implemented in a 0.25 μm digital CMOS technology. The converter operates at 10 MS/s with 9 bits, has a dynamic range of 80 dB, with 44.3 dB SNR, and dissipates a power of 478 mW, from a 2.5 V power supply.
Electronics, Circuits and Systems, 2002. 9th International Conference on; 02/2002
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ABSTRACT: The trade-offs between bandwidth, resolution and power in high
dynamic range pipeline analog-to-digital converters are studied when a
pure digital CMOS technology is considered. Calibration techniques are
presented to achieve the required resolution, and the design
optimization methodology of the relevant pipeline building blocks are
discussed. An example of a 15-bit 10 Ms/s analog-to-digital pipeline
converter implemented in a 0.35 μm digital CMOS technology is
presented
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: High-resolution pipeline analog-to-digital converters usually
employ digital correction techniques to relax the requirements of the
flash comparators, thus improving the performance of the converter. This
paper exploits the same used common digital techniques to the class of
non-linear ADCs, and in the special case of a true logarithmic pipeline
converter. While the logarithmic operation is achieved by replacing the
linear operations of subtraction and multiplication by simple scaling
operations, the use of digital error correction allows to achieve high
resolution and high dynamic range. An example is given to illustrate the
proposed technique
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on; 02/2001
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ABSTRACT: This paper discusses the use of symbolic methods applied to the
design automation of non-linear data converters. The proposed approach
is an extension of an already proved methodology, for the symbolic
synthesis of linear data converters, by both introducing non-linear
characteristics in a modified signal flow graph approach and reusing
library functional blocks by an appropriate retargeting for the new
design goals. The design process is here exemplified with recently
proposed architectures for logarithmic data converters
Electronics, Circuits and Systems, 1998 IEEE International Conference on; 02/1998
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ABSTRACT: A new technique for realising in MOS technology a logarithmic
analog-to-digital (A/D) converter employing a two-step flash
architecture suitable for high-frequency operation is described. While
the logarithmic operation is achieved by replacing the linear operations
of subtraction and multiplication by simple scaling operations, the use
of digital error correction techniques allows one to achieve high
resolution and high dynamic range performance. An example is given to
illustrate the proposed technique
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on; 09/1995
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ABSTRACT: This paper describes the design and integrated circuit
implementation of a logarithmic digital-to-analogue converter employing
a digitally-controlled current attenuator whose accuracy depends solely
on the matching of transistors. An 8-bit resolution, 80 dB dynamic range
prototype chip fabricated in a 1.2 μm digital CMOS technology
occupies 1.5 mm<sup>2</sup> and at 5 V supply and 1 MHz conversion rate
dissipates 6 mW
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on; 01/1995
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ABSTRACT: A mixed analog-digital (A/D) integrated circuit (IC) specifically
designed to realize the audio processing functions needed for a portable
radiotelephone (PRT) application is described. Multirate signal
processing techniques are used to reduce the capacitance spread, and
hence the overall silicon area, of the chip, as well as to minimize the
settling requirements of the amplifiers for lower power consumption.
This, together with programmable power-saving control circuitry also
incorporated on-chip, considerably extends the lifetime of the battery.
A semicustom design methodology is employed to implement such an
application-specific integrated circuit (ASIC) in a 3-μm CMOS
double-poly processing technology. Experimental results are presented to
demonstrate the correct operation and functionality of the prototype
chips
IEEE Journal of Solid-State Circuits 06/1993; · 3.23 Impact Factor
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ABSTRACT: New techniques for realizing CMOS logarithmic analog-to-digital
(A/D) converters employing pipeline and algorithmic architectures are
described. This is achieved by replacing the operations of
subtraction/addition and multiplications in their linear counterparts by
simple scaling operations in the logarithmic domain. Logarithmic
pipeline A/D converters are more appropriate for high-frequency
applications whereas logarithmic algorithmic A/D converters are
particularly suitable for compact, low-cost designs. Examples are given
to illustrate the proposed techniques
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on;
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ABSTRACT: This paper describes an innovative analog IC layout generation tool based on evolutionary computation techniques. The proposed approach starts by a high level layout description (template), which is independent from technology, although including expert knowledge as placement and routing constrains. Then, based on the set of constrain rules provided by the designer through the template, the layout is automatically generated using an evolutionary kernel. Additionally, a module generated is also included in order to allow the automatic generation of different instances for each device in the layout template, therefore, automatically enlarging the solution search space. The LAYGEN tool is here presented and demonstrated for the layout generation of typical circuit structures
Research in Microelectronics and Electronics 2006, Ph. D.;
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ABSTRACT: This paper describes digitally-controlled analogue signal
processing and conversion techniques based on a logarithmic current
attenuator building block fully compatible with digital CMOS technology,
and whose accuracy depends solely on the matching of transistors.
Application examples given to illustrate the proposed techniques include
logarithmic analogue-to-digital and digital-to-analogue conversion and
automatic gain control, functions commonly used in various
communications and instrumentations applications
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on;
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ABSTRACT: This paper presents the system-level design of a wireless receiver's analog baseband front-end, which satisfies the standards of 4G mobile communications. An analysis of different topologies for wireless receivers suited for multi-standard purposes is performed. The Zero-IF architecture is chosen and design issues of analog baseband blocks are outlined, regarding a multi-standard solution. A detailed system-level analysis on the analog-to-digital converter block, based on a Sigma-Delta topology, is presented as an example of a reconfigurable analog block.
