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Y. Kim,
S.C. Oh,
W.C. Lim,
J.H. Kim,
W.J. Kim,
J.H. Jeong,
H.J. Shin,
K.W. Kim,
K.S. Kim,
J.H. Park,
S.H. Park,
H. Kwon,
K.H. Ah,
J.E. Lee,
S.O. Park,
S. Choi, H.K. Kang,
C. Chung
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ABSTRACT: 28nm MTJ for 8~16Gb MRAM device has been successfully integrated with special patterning & etch technique. Resistance (R) separation between high and low R states was 15.2σ, comparable to that for 80nm MTJ cells. Thermal stability factor (Δ) followed prediction fairly well, and MTJ with free layer (FL) of 25Å and aspect ratio (AR) of 3 showed Δ of 56. In order to realize sub-30nm MRAM device, a novel FL with substantially low critical current density (J<sub>c</sub>) or revolutionary MTJ scheme needs to be developed.
VLSI Technology (VLSIT), 2011 Symposium on; 07/2011
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ABSTRACT: The high frequency drain current noise in nanoscale MOSFETs is carefully measured and compared with the shot and the thermal noise levels in all operating regions. For the first time, the shot noise characteristics are observed in the strong inversion region around-10 nm MOSFETs.
VLSI Technology, 2009 Symposium on; 07/2009
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J-T. Park,
H-S. Park, H-K. Kang,
J-S. Hong,
H. Cha,
E-J. Woo,
J-W. Kim,
M-J. Kim,
W. Boos,
S. Lee,
K-H. Park
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ABSTRACT: A gene, treX, encoding a debranching enzyme previously cloned from the trehalose biosynthesis gene cluster of Sulfolobus solfataricus P2 was expressed in Escherichia coli as a His-tagged protein and the biochemical properties were studied. The specific activity of the S. solfataricus debranching enzyme (TreX) was highest at 75°C and pH 5.5. The enzyme exhibited hydrolysing activity toward α-1,6-glycosidic linkages of amylopectin, glycogen, pullulan, and other branched substrates, and glycogen was the preferred substrate. TreX has a high specificity for hydrolysis of maltohexaosyl α-1,6-β-cyclodextrin, indicating the high preference for side chains consisting of 6 glucose residues or more. The enzyme also exhibited 4-α-sulfoxide-glucan transferase activity, catalysing transfer of α-1,4-glucan oligosaccharides from one chain to another. Dimethyl sulfoxide (10%, v/v) increased the hydrolytic activity of TreX. Gel permeation chromatography and sedimentation equilibrium analytical ultracentrifugation revealed that the enzyme exists mostly as a dimer at pH 7.0, and as a mixture of dimers and tetramers at pH 5.5. Interestingly, TreX existed as a tetramer in the presence of DMSO at pH 5.5–6.5. The tetramer showed a 4-fold higher catalytic efficiency than the dimer. The enzyme catalysed not only intermolecular trans-glycosylation of malto-oligosaccharides (disproportionation) to produce linear α-1,4-glucans, but also intramolecular trans-glycosylation of glycogen. The results presented in this study indicated that TreX may be associated with glycogen metabolism by selective cleavage of the outer side chain.
07/2009; 26(1-2):76-85.
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H.-J. Kim,
S.C. Oh,
J.S. Bae,
K.T. Nam,
J.E. Lee,
S.O. Park,
H.S. Kim,
N.I. Lee,
U-In Chung,
J.T. Moon, H.K. Kang
[show abstract]
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ABSTRACT: Toggle switching mode MRAM is tested and characterized with respect to the free- and pinned-layer material and thickness. With magnetization curves, we were able to find the optimum thickness combinations of free-layer and spacer materials. For CoFeB where the intrinsic anisotropy field ( Hi) is about 20-30 Oe, one needs to have a reasonably high exchange coupling field (Hex) to ensure large switching margin. In case of an NiFe/Ru/NiFe free-layer, Hi is usually much smaller than Hex, so that further decrease of Hex between two magnetic layers is needed. The pinned-layer roughness and thickness are other factors to be optimized to reduce the toggle switching field. High cell aspect ratio ≥3.0 helps to minimize the switching distribution and enhance the switching stability.
IEEE Transactions on Magnetics 11/2005; · 1.36 Impact Factor
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H.-J. Kim,
J.E. Lee,
I.G. Baek,
Y.K. Ha,
J.S. Bae,
S.C. Oh,
S.O. Park,
U-In Chung,
N.I. Lee, H.K. Kang,
J.T. Moon
[show abstract]
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ABSTRACT: The dependence of the switching field distribution of magnetic random access memory cells on film roughness, saturation magnetization, film thickness, and cell aspect ratio is discussed. We found that a flat interface between the tunnel oxide and the magnetic film is very important in suppressing switching field variation. For free-layer materials, NiFe, CoNiFe, CoFeB, and lamellar structures are examined. By trying various compositions of these materials, we have improved switching characteristics with small saturation magnetization and small thickness. Good results with lamellar structures suggest that the suppression of the grain growth in the ferromagnetic layer is another effective way to get enhanced switching characteristics.
IEEE Transactions on Magnetics 08/2004; · 1.36 Impact Factor
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Y.K. Ha,
J.E. Lee,
H.-J. Kim,
J.S. Bae,
S.C. Oh,
K.T. Nam,
S.O. Park,
N.I. Lee, H.K. Kang,
U.-I. Chung,
J.T. Moon
[show abstract]
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ABSTRACT: Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: Chemical-vapor-deposited(CVD) Cu film was successfully demonstrated as a seed layer for Cu electroplating, by using atomic-layer-deposited(ALD) Ru as a glue layer on ALD WNC barrier metal. Low via resistance of below 3Ω/via was obtained in 0.13 μm via chains, which was built in SiOC (k=2.9) intermetal dielectric. The adhesion between WNC and CVD Cu. estimated by mELT, was significantly improved by the insertion of ALD Ru and HR-XTEM analysis showed no interfacial layers at both Cu/Ru and Ru/WNC interfaces. In addition, Ru was found to promote the 2-D planar growth of CVD Cu film rather than the 3-D island growth.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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I.W. Cho,
B.R. Lim,
J.-H. Kim,
S.S. Kim,
K.C. Kim,
B.J. Lee,
G.J. Bae,
N.I. Lee,
S.H. Kim,
K.W. Koh, H.-K. Kang,
M.K. Seo,
S.W. Kim,
S.H. Hwang,
D.Y. Lee,
M.C. Kim,
S.D. Chae,
S.A. Seo,
C.W. Kim
[show abstract]
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ABSTRACT: We have successfully integrated 8M bits Localized ONO Memory (LONOM) for the embedded nonvolatile memory using 0.13um standard logic process with 5-level Cu metallization. which has a small cell size of 0.276UM and the simplest cell array structure. Without any special algorithm, the localized storage layer of the LONOM can satisfy the essential features for an embedded memory solution, such as low program current. disturb-free read operation and good endurance characteristics. The read speed is as high as 60MHz at V<sub>cc</sub>=0.9V, 85°C and the current consumption is lower than 5mA at Vcc = 1.4V.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: For the first time, we evaluated the long-term lifetime for Hafnium based high-k dielectrics such as HfO<sub>2</sub> and HfO<sub>2</sub>-Al<sub>2</sub>O<sub>3</sub> laminates at 25· · and 125· · in capacitor applications. The extracted Weibull slope of HfO<sub>2</sub> T<sub>BD</sub> distribution shows thickness dependence to be explained by percolation theory. We demonstrate that elevated operation temperature further accelerates HfO<sub>2</sub> breakdown than HfO<sub>2</sub>-Al<sub>2</sub>O<sub>3</sub> laminates, resulting from severe temperature dependent leakage currents due to different conduction mechanisms.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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ABSTRACT: High-quality single-walled carbon nanotubes (SWNTs) have been synthesized over Fe−Mo/MgO catalyst by catalytic decomposition of ethylene at 800 °C. The produced carbon material primarily consists of a SWNT bundle with few defects and a very small amount of amorphous carbon coating. The diameter of an individual SWNT is in the range of 0.7−2.8 nm. The as-synthesized SWNTs have a high yield of over 550% relative to the weight of Fe−Mo metal in the Fe−Mo/MgO catalyst. Our results show that ethylene can be a very ideal carbon source for the synthesis of SWNTs. We suggest that catalytic decomposition of ethylene over Fe−Mo/MgO catalyst can promise a large-scale production of high-quality SWNTs.
01/2004;
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I.G. Baek,
J.E. Lee,
H.-J. Kim,
Y.K. Ha,
J.S. Bae,
S.C. Oh,
S.O. Park,
U.-I. Chung,
N.I. Lee, H.K. Kang,
J.T. Moon
[show abstract]
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ABSTRACT: The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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J.H. Yi,
Y.H. Ha,
J.H. Park,
B.J. Kuh,
H. Horii,
Y.T. Kim,
S.O. Park,
Y.N. Hwang,
S.H. Lee,
S.J. Ahn,
S.Y. Lee,
J.S. Hong,
K.H. Lee,
N.I. Lee, H.K. Kang,
U-In Chung,
J.T. Moon
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ABSTRACT: We have developed a novel cell structure of PRAM with metal interlayer. This novel structure has been proposed to solve the over-programming fail. We have examined the cause of over-programming by simulation of the phase transition of chalcogenide and successfully demonstrated reliable cell operation of this novel structure in writing current level, crystallization speed, and endurance. It can be explained by a model in which the metal interlayer is a local heat sink and the top GST layer is a thermal insulator.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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Advanced Materials 07/2003; 15(14):1172 - 1176. · 13.88 Impact Factor
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J.-H. Kim,
I.W. Cho,
G.J. Bae,
S.S. Kim,
K.C. Kim,
S.H. Kim,
K.W. Koh,
N.I. Lee, H.-K. Kang,
K.-P. Suh,
S.T. Kang,
M.K. Seo,
S.H. Lee,
M.C. Kim,
I.S. Park
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ABSTRACT: A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 μm standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 μm<sup>2</sup> Local SONOS NVM cell, which has 20 μs program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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M.C. Sun,
M.J. Kim,
J.-H. Ku,
K.J. Roh,
C.S. Kim,
S.P. Youn,
S.-W. Jung,
S. Choi,
N.I. Lee, H.-K. Kang,
K.P. Suh
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ABSTRACT: For sub-50 nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel silicide on 50 nm gate thermally-robust up to 600°C during device fabrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30 nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90 nm MOSFETs is successfully integrated with NiTa SALICIDE process.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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K.-W. Lee,
S.G. Lee,
W.J. Park,
B.J. Oh,
J.H. Kim,
S.J. Lee,
K.K. Park,
I.G. Kim,
J.H. Chung,
K.T. Lee,
Y.J. We,
W.S. Song,
S.R. Hah, H.-K. Kang,
K.-P. Suh
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ABSTRACT: Integrating FSG dual damascene interconnects using MSQ-based sacrificial via filler has been previously shown. When applying such via filler to a Cu/low-k OSG integration, however, the requisite O<sub>2</sub>-ashing induces an inevitable damage to the low-k OSG due to the challenge in selectively eliminating such filler using conventional wet chemistry. By employing an inorganic HSQ that can readily be removed per dilute fluoric acid cleaning in low-k OSG structure, we demonstrated not only a more viable technology with lower defect density at each process step, e.g., photolithography and etching, but also a simpler process that selectively removes the filler material relative to the existing technology based on MSQ and/or organic fillers.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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K.-C. Park,
I.-R. Kim,
B.-S. Suh,
S.-M. Choi,
W.-S. Song,
Y.-J. Wee,
S.-G. Lee,
J.-S. Chung,
J.-H. Chung,
S.-R. Hah,
J.-H. Ahn,
K.-T. Lee, H.-K. Kang,
K.-P. Suh
[show abstract]
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ABSTRACT: An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
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W.S. Song,
C.S. Lee,
K.C. Park,
B.S. Suh,
J.W. Kim,
S.Y. Kim,
Y.J. Wee,
S.M. Choi, H.-K. Kang,
S.U. Kim,
K.P. Suh
[show abstract]
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ABSTRACT: By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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C.B. Oh, H.S. Kang,
H.J. Ryu,
M.H. Oh,
H.S. Jung,
Y.S. Kim,
J.H. He,
N.I. Lee,
K.H. Cho,
D.H. Lee,
T.H. Yang,
I.S. Cho,
H.K. Kang,
Y.W. Kim,
K.P. Suh
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ABSTRACT: Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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ABSTRACT: A Ge-redistributed poly-Si/SiGe stack gate (GRPSG) has been
proposed to improve the current performance of PMOS without the
degradation of NMOS for sub-0.1 μm CMOSFETs with ultrathin gate
oxide. Ge diffusion into the poly-Si layer was promoted more by ion
implantation of N-type dopants such as P and As rather than P-type
dopants. NMOS and PMOS had different Ge concentrations at the interface
between gate electrode and gate oxide by an additional anneal to
redistribute the Ge profile. The current performance of NMOS with GRPSG
with low Ge content (<5%) was not degraded, while that of PMOS with
GRPSG with high Ge content (>20%) was improved due to suppression of
the poly-depletion effect and boron penetration. In addition, the gate
reoxidation was modified to reduce G<sub>m</sub> degradation by reduced
gate bird's beak. High-performance 70 nm-CMOSFETs were successfully
fabricated using the simple GRPSG process
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on; 02/2001
