M.V. Rao

Publications (18)15.98 Total impact

• Article: Stability and 2-D Simulation Studies of Avalanche Breakdown in 4H-SiC DMOSFETs With JTE

  T. Okayama, S.D. Arthur, R.R. Rao, K. Kishore, M.V. Rao
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  ABSTRACT: In this paper, the stability of n-channel 4H-silicon carbide (SiC) DMOSFETs with junction termination extension (JTE) was assessed by measuring the breakdown voltage (BV) of these devices before and after bias stress at a high temperature. The BV slumped after the DMOSFET was bias stressed at 1200 V for 2 h at 175degC, and the slumped BV dynamically recovered to the prestress value during the poststress period. Computer simulation suggests that the BV slump and its recovery are dominated by the positive charge trapping/detrapping phenomena at the SiC/fleld oxide interface in the JTE structure, rather than the trapping/detrapping at the SiC/gate oxide interface in the cell structure. A positive interface charge of approximately one-third of the sheet dopant concentration of the JTE region, lowers BV by 150 V, which is the typical measured BV slump of the DMOSFETs of this paper.
  IEEE Transactions on Electron Devices 03/2008; · 2.32 Impact Factor
• Conference Proceeding: Reliability of 4H-SiC DMOSFETs Evaluated by Bias Stressing

  T. Okayama, S.D. Arthur, J.L. Garrett, M.V. Rao
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  ABSTRACT: In this work, the threshold voltage (V_TH) of n-channel 4H-SiC double-implanted metal-oxide- semiconductor field effect transistors (DMOSFETs) was measured after different gate-bias-stress durations to determine if the bias-stress induces a shift in the V_TH.
  Device Research Conference, 2007 65th Annual; 07/2007
• Article: Characteristics of planar n-p junction diodes made by double-implantations into 4H-SiC

  J.B. Tucker, M.V. Rao, N.A. Papanicolaou, J. Mittereder, A. Elasser, A.W. Clock, M. Ghezzo, O.W. Holland, K.A. Jones
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  ABSTRACT: Double implantation technology consisting of deep-range acceptor followed by shallow-range donor implantation was used to fabricate planar n⁺-p junction diodes in 4H-SiC. Either Al or B was used as the acceptor species and N as the donor species with all implants performed at 700°C and annealed at 1650°C with an AlN encapsulant. The diodes were characterized for their current-voltage (I-V) and capacitance-voltage (C-V) behavior over the temperature range 25°C-400°C, and reverse recovery transient behavior over the temperature range 25°C-200°C. At room temperature, the B-implanted diodes exhibited a reverse leakage current of 5×10^-8 A/cm² at a reverse bias of -20 V and a carrier lifetime of 7.4 ns
  IEEE Transactions on Electron Devices 01/2002; · 2.32 Impact Factor
• Source

  Available from: 144.206.159.178

  Conference Proceeding: Maturing ion-implantation technology and its device applications inSiC

  M.V. Rao
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  ABSTRACT: Ion-implantation is an indispensable technique for planar selective area doping of SiC devices, because thermal diffusion of the desired dopants at temperatures where SiC doesn't decompose is not possible. Incongruent evaporation of Si from the SiC wafer during post-implantation annealing limits the maximum annealing temperature that can be used to repair the lattice damage and steer the implant into the substitutional lattice positions. Other problems include the nonstoichiometric disturbances caused by the ion-implantation, which result in non-uniform Si and C atom concentration and vacancy concentration depth distributions in the implanted region; and the difficulty in restoring the lattice quality back to the virgin level if as-implant lattice damage is of amorphous level. Ion-implantation in SiC needs to be performed at an elevated temperature in the range of 500 - 1000 °C. An additional problem is the deep ionization energies of the useful donor (~ 80 meV) and acceptor (> 240 meV) impurities in SiC, which limit the maximum carrier concentration . Results of donor, acceptor, and compensation species ion-implantations in 6H- and 4H-SiC are presented
  Semiconductor Device Research Symposium, 2001 International; 02/2001
• Conference Proceeding: Deep levels in ion implanted field effect transistors on SiC

  S. Mitra, M.V. Rao, K. Jones, X.W. Wang, N. Papanicolaou, S. Wilson
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  ABSTRACT: Silicon Carbide (SiC) is emerging as an important material for fabricating high power, high temperature and high frequency devices because it has high thermal conductivity, large saturation electron drift velocity, high electric breakdown field and excellent thermal stability. Ion implantation of donor and acceptor impurities into bulk SiC is an attractive method for making planar devices and it has been used to fabricate a variety of SiC based FETs in the past few years. However, the performance and reliability of these devices still remain a serious problem for industrial applications. This is due to channel/insulator or channel/substrate interface traps, which reduce the mobilities in MISFETs and MESFETs to values much lower than those measured in bulk material. Deep Level Transient Spectroscopy (DLTS) is an excellent way to evaluate these trap, but only a few studies have been done on the deep levels. In this work interface traps are studied in detail for two FET device structures: MISFET on p-type 6H-SiC and MESFET on semi-insulating (SI) bulk 4H-SiC. For MISFETs the traps at the gate insulator/semiconductor interface created during insulator deposition and for MESFETs, the traps at the channel/substrate interface introduced by the ion-implantation process are examined.
  Semiconductor Device Research Symposium, 2001 International; 02/2001
• Conference Proceeding: Ion-implantation doping of silicon carbide

  J. Gardner, A. Edwards, M.V. Rao, N. Papanicolaou, G. Kelner, O.W. Holland
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  ABSTRACT: Because of their commercial availability in bulk single crystal form, the 6H- and 4H- polytypes of SiC are gaining importance for high-power, high-temperature, and high-frequency device applications. Selective area doping is a crucial processing step in integrated circuit manufacturing. In Si technology, selective area doping is accomplished by thermal diffusion or ion-implantation. Because of the low diffusion coefficients of most impurities in SiC, ion implantation is indispensable in SiC device manufacturing. In this paper the authors present their results on donor, acceptor, and compensation implants in 6H-SiC.
  09/1997
• Article: High-energy (MeV) ion implantation and its device applications in GaAs and InP

  M.V. Rao
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  ABSTRACT: The work performed to date on the implantation of megaelectronvolt (MeV) energy ions of shallow donor (Si, S), shallow acceptor (Be), compensation (B, O, N, Fe, Co, Ti), and rare-earth (Er) species in III-V GaAs and InP compounds is reviewed. The optimum annealing conditions, the resulting carrier concentrations, and the lattice quality of the material are discussed. For the buried implants, the lattice damage and the electrical properties of the material are almost independent of the implant energy. For MeV Be⁺ implants the outdiffusion of Be during annealing is not observed, unlike in the case of shallow keV Be ⁺ implants. The MeV energy Fe⁺ or Co⁺ implants performed at 200°C into n-type InP, and Ti implants into p-type InP gave thermally stable buried high-resistance layers. The performance of microwave devices like vertical p-i-n, varactor, and mixer diodes and an optical device like a heterostructure laser made using MeV energy ion implantation is discussed. The results of MeV implantation in obtaining interdevice isolation of multilayer structures like HBTs are also discussed
  IEEE Transactions on Electron Devices 07/1993; · 2.32 Impact Factor
• Conference Proceeding: Fe and Ti compensation implants into n- and p- In_0.52Al_0.48A and p- InP

  J.M. Martin, M.V. Rao, J.B. Boos, O.W. Holland
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  ABSTRACT: Fe and Ti implantations were performed into n- and p- type InAlAs, respectively. Fe implants suffered a strong out-diffusion during annealing, whereas Ti implants showed only a slight in- and out- diffusion. The crystalline quality of the annealed material was very close to that of the virgin un-implanted sample, and resistivities higher than 10⁶ Ω-cm were obtained. MeV Ti implantations were performed into p-type InP. The Ti implant profiles showed almost no redistribution during annealing and the material had good crystalline quality after annealing. Resistivities near the intrinsic limit for InP were obtained
  Indium Phosphide and Related Materials, 1993. Conference Proceedings., Fifth International Conference on; 05/1993
• Conference Proceeding: MeV energy ion implantation and its device applications in InP

  R.K. Nadella, J. Vellanki, M.V. Rao
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  ABSTRACT: MeV energy Si, S, Be, B, Fe, and Co implantations were performed in the energy range 0.4-20 MeV to obtain buried/thick n- or p- or high-resistance layers in InP. The first four range statistics have been established for these dopants in this energy range. Optimum annealing conditions have been established. Electron concentrations as high as 2 × 10¹⁸ cm^-3 have been obtained. B, Fe, and Co implantations gave high resistivity layers. The usefulness of MeV implantation was demonstrated in the fabrication of vertical positive-intrinsic-negative (PIN) and varactor diodes
  Indium Phosphide and Related Materials, 1993. Conference Proceedings., Fifth International Conference on; 05/1993
• Article: DC characteristics of high-breakdown-voltage p-i-n diodes made by 20-MeV Si implantation in InP:Fe

  R.K. Nadella, J. Vellanki, M.V. Rao, H.B. Dietrich
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  ABSTRACT: A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n/sup +/ layer and a shallow p/sup +/ layer, respectively. The junction area of the device is 2.3*10/sup -5/ cm/sup 2/ and the intrinsic region thickness is approximately=3 mu m. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm/sup 2/ at -80 V, off-state capacitance of 2.2 nF/cm/sup 2/ at -20 V, and a DC incremental forward resistance of 4 Omega at 40 mA.< >
  IEEE Electron Device Letters 10/1992; · 2.85 Impact Factor
• Conference Proceeding: Vertical InP pin diode made by MeV energy Si implantation

  R.K. Nadella, J. Vellanki, M.V. Rao
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  ABSTRACT: To evaluate the potential of high-energy Si implantation in InP:Fe, the authors have fabricated a vertical p-i-n diode which is useful for high-power microwave switching. For high-power microwave switching, p-i-n diodes are preferred over FETs for their higher breakdown voltage, lower on-state resistance and lower off-state capacitance. Though a lateral structure is more convenient for monolithic integration, the vertical structure led to a better performance of epitaxially grown GaAs p-i-n diodes. A vertical p-i-n structure is preferable over a lateral structure due to the excessive surface conduction in the latter. Using epitaxially grown vertical GaAs p-i-n diodes, monolithic circuits like the 5-b phase shifter, the SP16T switch, and the variable attenuation limiter have been fabricated. Recently, using megaelectronvolt Si/S and kiloelectronvolt energy Be/P co-implantation in SI GaAs, vertical GaAs p-i-n diodes with favorable characteristics have been made
  Indium Phosphide and Related Materials, 1992., Fourth International Conference on; 05/1992
• Article: Metal-semiconductor-metal photodetector using Fe-implanted In0.53Ga0.47As

  M.V. Rao, S.M. Gulwadi, W.-P. Hong, C. Caneau, G.K. Chang, N. Papanicolaou
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  ABSTRACT: A two finger interdigitated metal-semiconductor-metal detector has been made using high-resistance Fe-implanted In_0.53Ga_0.47As material grown on InP:Fe. The fingers are 30 mu m long with 1 mu m width and 1.5 mu m separation. The breakdown voltage of the device is 5V. At 2 V bias, the device has a dark current of 250 nA and a DC responsivity of 0.375 A/W at 1.3 mu m. The full width at half maximum of the response of the detector at 1.3 mu m is 260 ps.
  Electronics Letters 02/1992; · 0.96 Impact Factor
• Article: Rapid isothermal annealing of high- and low-energy ion-implanted InP and In0.53Ga0.47As

  M.V. Rao
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  ABSTRACT: Rapid isothermal annealing (RIA) was performed on 0.5-16-MeV Si ⁺, 1-MeV Be⁺, and 150-keV Ge⁺ implanted InP:Fe and 380-keV Fe⁺ implanted InGaAs. Annealings were performed in the temperature range 800-925°C using an InP proximity wafer in addition to the Si₃N₄ dielectric cap. Dopant activations close to 100% were obtained for 3×10¹⁴ cm^-2 Si⁺ and 2×10¹⁴ cm^-2 Be⁺ implants in InP:Fe. For the elevated temperature (200°C) 1×10¹⁴ cm^-2 Ge⁺ implant, a maximum of 50% activation was obtained. No redistribution of dopant was observed for Si and Ge implants due to annealing. However, redistribution of dopant was seen for Be and Fe implants due to annealing. Phosphorous coimplantation has helped to eliminate the Be in-diffusion problem in InP, but did not help to reduce Fe in-diffusion and redistribution in InGaAs. Using an RIA cycle with low temperature and short duration is the only solution to minimize Fe redistribution in InGaAs
  IEEE Transactions on Electron Devices 02/1992; · 2.32 Impact Factor
• Article: GaAs vertical PIN diode using MeV implantation

  M.V. Rao, W. Kruppa, H.B. Dietrich, S.C. Binari, J.B. Boss
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  ABSTRACT: For high-power microwave switching, PIN diodes are preferred over MESFETs due to their higher breakdown voltage, lower on-state resistance, and lower off-state capacitance. The authors have fabricated vertical PIN diodes using MeV Si/S coimplantation and keV Be/P coimplantation into undoped semi-insulating GaAs to obtain buried n⁺ and surface p⁺ regions respectively. An exploratory device with a 500*500 mu m² junction area and a 3 mu m thick intrinsic region has a breakdown voltage of 70 V, reverse leakage current density of 40 mu A/cm² at 20 V, an off-state capacitance of 3.9 nF/cm² and a DC forward resistance of 2.4 Omega at 100 mA.
  Electronics Letters 12/1991; · 0.96 Impact Factor
• Conference Proceeding: Implantation of high-energy Si and Be ions in InP and low-energytransition metal ions in InGaAs

  M.V. Rao, R.K. Nadella, S.M. Gulwadi
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  ABSTRACT: High-energy ion implantation in compound semiconductors, an economical alternative to the epitaxial growth technique for fabrication of devices that need thick or buried active layers is discussed. High-energy Si implantations in InP yield buried layers with high carrier concentration and low defect density as long as the implant dose is less than the critical dose that makes the material amorphous. Elevated temperature implants need to be used to extend the critical dose. Compensation of the surface side tail of the implant profile is necessary to obtain the sharp carrier concentration depth profiles that are necessary for many device applications. The Be/P coimplantation is useful for obtaining buried p-type profiles without any broadening caused by Be in-diffusion. The Fe implantation is useful for obtaining high resistance regions in InGaAs
  Indium Phosphide and Related Materials, 1991., Third International Conference.; 05/1991
• Article: High-sensitivity, high-speed InGaAs photoconductive detector

  M.V. Rao
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  ABSTRACT: In_0.53Ga_0.47As photoconductive detectors with low dark current and high speed are obtained by multiple energy H bombardment on p-type material. The dark current of the detectors is 10 mu A, the detectivity at 1.31 mu m is 1 A/W and the bandwidth is 1.8 GHz at a source-drain bias of 6 V for 5 mu m contact spacing.
  Electronics Letters 06/1990; · 0.96 Impact Factor
• Article: Ion implantation of Si in semi-insulating In0.53Ga0.47As:Fe

  M.V. Rao, W. Kruppa
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  ABSTRACT: Ion implantation of Si in semi-insulating In0.53Ga0.47As:Fe was discussed. Electrical activation of more than 100%, a broad implant profile and an average electron mobility of 3000 cm2/Vs are observed in layers implanted with a dose of 2 × 1013 cm¿2 at 260 keV and annealed at 670°C for 15 min. The results of photoluminescence measurements are also presented.
  Electronics Letters 02/1986; · 0.96 Impact Factor
• Article: Nitrogen and phosphorus implanted MESFETs in semi-insulating 4H-SiC

  J.B. Tucker, S. Mitra, N. Papanicolaou, A. Siripuram, M.V. Rao, O.W. Holland
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  ABSTRACT: Nitrogen and phosphorus ion implantation were used to fabricate 2 μm gate length, n-channel Metal-Semiconductor Field-Effect-Transistors (MESFETs) in semi-insulating bulk 4H-SiC. In order to create the channel region, either nitrogen or phosphorus ion-implantations was performed to a depth of 300 nm at room temperature to a volumetric concentration of 5×1017 cm−3. The source/drain regions were created by nitrogen implantation to a volumetric concentration of 2×1019 cm−3, regardless of the species used for the channel implantation. Annealing for a duration of 15 min at 1450 °C (for nitrogen-implanted channels) or 1500 °C (for phosphorus-implanted channels) activated the implants. This study utilized aluminum Schottky gates for the FETs. Both the nitrogen and phosphorus-implanted channel MESFETS exhibited pinch-off voltages at approximately 18 V and the drain saturation currents between 30 and 40 mA.
  Diamond and Related Materials. 11:392-395.