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ABSTRACT: The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE; 06/2005
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ABSTRACT: The problem of testing the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs) is addressed in This work. The considered fault model comprises deviations in the nominal values of CAB programmable capacitors, deviations in the programmable gains of CAB input amplifiers and stuck-on/stuck-open faults in CAB switches. The problem of test stimuli generation is solved, in a first approach, by using the oscillation test strategy (OTS), which is associated to a test response analysis external to the device under test. In a second approach, a built-in self-test (BIST) scheme is proposed by associating to the OTS an output response analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.
Test Conference, 2004. Proceedings. ITC 2004. International; 11/2004
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ABSTRACT: Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the whole SoC. This paper discusses the impact on the global system testing time of an analog BIST method based on digital reuse. Experimental results show that the reuse of digital blocks to test analog signals is indeed a very efficient strategy, even under power constraints, as long as the BIST technique reduces the analog testing time.
Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on; 10/2004
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ABSTRACT: The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE; 05/2004
